This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
mp3設(shè)計(jì)程序資料，采用c語(yǔ)言編寫(xiě)。
README file for
yampp-3 source code 2001-05-27
This is the current state of the yampp-3 source code, 2001-05-27.
This code is intended to run on Rev. B of the yampp-3 PCB, but can
ofcourse be used on compatible systems as well.
It still uses the "old" song selection system as the yampp-2.
However, the disk handling routines has improved a lot and the
obviosly, the new VS1001 handling has been put in.
The codesize is almost at it s maximum at 1F40 bytes.
A .ROM file is included if you don t have the compiler set up.
For now, the documentation is in the code
cpress usb 芯片Vender 處理固件。
The purpose of this software is to demonstrate how
to implement vendor specific commands.
The following vendor specific commands are implemented:
A0 Firmware Upload/Download
A2 EEProm Load
A3 External Ram Load
A4 Set I2C Addr
A5 Get IIC Type (1 Byte or 2 Byte EEPROM)
A6 Get Chip Rev
A8 Renumerate
CF VHDL
The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
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