教你寫Makefile 什么是makefile？或許很多Winodws的程序員都不知道這個(gè)東西，因?yàn)槟切￤indows的IDE都為你做了這個(gè)工作，但我覺得要作一個(gè)好的和professional的程序員，makefile還是要懂。這就好像現(xiàn)在有這么多的HTML的編輯器，但如果你想成為一個(gè)專業(yè)人士，你還是要了解HTML的標(biāo)識(shí)的含義。特別在Unix下的軟件編譯，你就不能不自己寫makefile了，會(huì)不會(huì)寫makefile，從一個(gè)側(cè)面說明了一個(gè)人是否具備完成大型工程的能力。
標(biāo)簽： Makefile
上傳時(shí)間： 2013-10-12
上傳用戶：zhoujunzhen
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.HTML Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.HTML Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
基于VHDL的FPGA和Nios II 實(shí)例精煉【作者：劉福奇；出版社：北京航空航天大學(xué)出版社】（本書優(yōu)酷視頻地址：http://www.youku.com/playlist_show/id_5882081.HTML） 內(nèi)容簡(jiǎn)介：本書分為4個(gè)部分：Quartus Ⅱ軟件的基本操作、VHDL語法介紹、FPGA設(shè)計(jì)實(shí)例和Nios Ⅱ設(shè)計(jì)實(shí)例；總結(jié)了編者幾年來的FPGA設(shè)計(jì)經(jīng)驗(yàn)，力求給初學(xué)者或是想接觸這方面知識(shí)的讀者提供一種快速入門的方法；適合電子相關(guān)專業(yè)的大學(xué)生、FPGA的初學(xué)者以及對(duì)FPGA有興趣的電子工程師。初學(xué)者可以按照步驟學(xué)習(xí)。本書中提及到時(shí)間計(jì)算問題，不光提出有時(shí)間戳的方法， 還介紹了一種通過讀取定時(shí)器的寄存器來計(jì)算時(shí)間的方法。其實(shí)，有人認(rèn)為，本書最好的部分是：DMA的實(shí)現(xiàn)說明（本書從3個(gè)方面講述了DMA的使用）。現(xiàn)在學(xué)習(xí)Verilog HDL的人或許比較多，但是用VHDL的人可以學(xué)習(xí)下，這本書還是很不錯(cuò)的。
上傳時(shí)間： 2014-07-10
上傳用戶：米米陽123
LineWatcher dials your ISP, keeps your connection alive and logs errors. Originally distributed as freeware, this program counts over 10.000 downloads since its first release in 2001. See home page http://www.reseau.org/linewatcher/index.HTML
標(biāo)簽： your LineWatcher distributed connection
上傳時(shí)間： 2015-01-10
上傳用戶：songyue1991
This simple SDI Notepad-like application demonstrates how, taking advantage of the MFC support for Unicode, to Turkmenize labels of the specified menu items. Actually, Turkmen is not supported by Windows 2000, therefore, to create such resources as menu so that strings in Turkmen could be displayed I had to invent an additional technique 這是一個(gè)與記事本類似的簡(jiǎn)單的SDI應(yīng)用程序，演示了怎樣使用MFC來支持 Unicode，對(duì)指定的菜單條目進(jìn)行Turkmenize標(biāo)簽化。實(shí)際上，Windwos 2000并不支持Turknen,因此,創(chuàng)建了那些菜單資源以便那些字符串可以在Turknen中顯示,為此我必須開發(fā)其它的技術(shù)。 來源: http://www.codeguru.com/advancedui/SDI_Note.HTML
標(biāo)簽： Notepad-like demonstrates application advantage
上傳時(shí)間： 2013-11-26
上傳用戶：txfyddz
I have written this article to capture a Windows image into a bitmap file that will support all PaintBrush tools and Thumbnail Views of Windows Explorer. I have found many programmers suffering from this problem, including me, until I wrote this article. 捕獲一個(gè)窗口圖像并存入一個(gè)支持MS畫筆的位圖文件中 我寫的這篇文章介紹了捕獲一個(gè)窗口圖像并存入一個(gè)支持所有畫筆和Windows Explorer的位圖文件中。 我發(fā)現(xiàn)許多程序員因這個(gè)問題而煩惱,包括我在內(nèi),直到我寫了這篇文章。 來源: http://www.codeguru.com/bitmap/WndToBmpFile.HTML
標(biāo)簽： article Windows capture written
上傳時(shí)間： 2015-01-10
上傳用戶：hzy5825468
Displaying a large bitmap file on a dialog box, in its original size, is quite difficult in the VC++ environment. However, it is possible to display a large bitmap to a predefined area of the dialog by using the StretchBlt( ) function.The major disadvantage of this is that the clarity of the image will be lost. Check out this article for displaying large bitmaps into the desired area of your dialog box in its original size with a scrolling technique used to show the entire bitmap. 滾動(dòng)顯示位圖 在VC++環(huán)境下，在一個(gè)對(duì)話框中顯示一個(gè)原始尺寸的大小的位圖文件相當(dāng)是困難的。然而,通過使用 StretchBlt()函數(shù)一個(gè)給定的區(qū)域顯示一個(gè)大的位圖是可能的。主要的缺點(diǎn)是圖像將會(huì)失真。看了這篇通過卷動(dòng)技術(shù)顯示整個(gè)位圖技術(shù)的文章，你將能夠以它的原始尺寸在給定對(duì)話框的區(qū)域內(nèi)顯示一個(gè)大位圖。 來源: http://www.codeguru.com/bitmap/ScrollBitmap.HTML
標(biāo)簽： Displaying difficult original bitmap
上傳時(shí)間： 2014-01-05
上傳用戶：yiwen213
BabelKit是一個(gè)通用多語言數(shù)據(jù)庫代碼表的接口。它接收維護(hù)使用多語言的多個(gè)數(shù)據(jù)庫代碼定義集中的所有編程工作。代碼管理和翻譯頁可以讓開發(fā)人員定義新的虛擬代碼表，新語言，輸入所有代碼和它的描述，再將它們翻譯成所有相關(guān)的語言。Perl和PHP類可以檢索代碼描述，并自動(dòng)地用用戶語言生成HTML代碼選擇元素。這簡(jiǎn)化了Web站點(diǎn)及數(shù)據(jù)庫的國際化和本地化。
標(biāo)簽： BabelKit 代碼 多語言 數(shù)據(jù)庫
上傳時(shí)間： 2014-12-01
上傳用戶：清風(fēng)冷雨
一個(gè)購物網(wǎng)站，包含本標(biāo)準(zhǔn)項(xiàng)目文檔．后臺(tái)數(shù)據(jù)庫連接．所以 演示的時(shí)候數(shù)據(jù)庫連接不到． 不過代碼完整．已通過測(cè)試．a(chǎn)sp,javascript,vbscript,HTML
標(biāo)簽： 網(wǎng)站
上傳時(shí)間： 2013-12-22
上傳用戶：ynsnjs
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