基于FPGA設(shè)計(jì)的相關(guān)論文資料大全 84篇用FPGA實(shí)現(xiàn)FFT的研究
劉朝暉 韓月秋
摘 要 目的 針對(duì)高速數(shù)字信號(hào)處理的要求，給出了用現(xiàn)場(chǎng)可編程門陣列(FPGA)實(shí)現(xiàn)的
快速傅里葉變換(FFT)方案.方法 算法為按時(shí)間抽取的基4算法，采用遞歸結(jié)構(gòu)的塊浮點(diǎn)運(yùn)
算方案，蝶算過程只擴(kuò)展兩個(gè)符號(hào)位以適應(yīng)雷達(dá)信號(hào)處理的特點(diǎn)，乘法器由陣列乘法器實(shí)
現(xiàn).結(jié)果 采用流水方式保證系統(tǒng)的速度，使取數(shù)據(jù)、計(jì)算旋轉(zhuǎn)因子、復(fù)乘、DFT等操作協(xié)
調(diào)一致，在計(jì)算、通信和存儲(chǔ)間取得平衡，避免了瓶頸的出現(xiàn).結(jié)論 實(shí)驗(yàn)表明，用FPGA
實(shí)現(xiàn)高速數(shù)字信號(hào)處理的算法是一個(gè)可行的方案.
關(guān)鍵詞 離散傅里葉變換； 快速傅里葉變換； 塊浮點(diǎn)運(yùn)算； 可編程門陣列
分類號(hào) TP39； TN957.511
Implementation of FFT with FPGA Technology
Liu Zhaohui Han Yueqiu
(Department of Electronics Engineering, Beijing Institute of Technology, Beijing 100081)
Abstract Aim To propose a scheme for implementing FFT with FPGA in accor-dance with the
requirement for high speed digital signal processing. Methods The structure of FPGA and
requirement of system were considered in the experiment, radix-4 algorithm of DIT and recursive
structure were adopted. The group float point arithmetic operation was used in the butterfly and the
array multiplier was used to realize multiplication. Results The pipeline pattern was used to ensure
the system speed, it made fetching data, calculating twiddle factor, complex multiplication and D
標(biāo)簽：
fpga
上傳時(shí)間：
2022-03-23
上傳用戶：
