·詳細說明：外掛硬盤和FLASH的MP3播放器解決方案，用C和匯編編寫，并附帶有電路原理圖- Outside hangs the hard disk and the FLASH MP3 player solution, with C and the assembly compilation, and has the electric circuit schematic diagram in pass
上傳時間： 2013-06-12
上傳用戶：yangbo69
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標簽： 數字電源
上傳時間： 2013-10-16
上傳用戶：dddddd
QSP-12是一款性/價比極高的直接使用USB通訊協議而開發的三星單片機專用編程器。不同于傳統采用USB轉RS232的編程器，直接使用USB通訊協議的QSP-12更快更可靠！配合精心優化設計的PC客戶端編程（燒錄）軟件，實現了業界最高的編程性能。自動燒錄S3F9454（包含擦除/編程/校驗/寫Smart option/Read protect/LDC protect/Hard Lock）只須0.7秒，代碼越小，燒錄越快；代碼越大，優勢越明顯！ 編程器采用小巧而堅實的烤漆鐵質外殼設計，具有極高的耐用性和抗電磁干擾能力，配備防止反插的RJ-11專業在線編程接口，確保您在使用過程中沒機會出錯。QSP-12快速可靠的編程（燒錄）能力，無論是您在產品開發、量產，還是在產品的現場升級階段，它都能給您帶來前所未有高效、可靠的編程體驗！在現今人力成本日益高漲的時代，為您贏得更多優勢！ QSP-12特點： 直接使用USB通訊，更快、更可靠 無需用戶設定編程電壓，更安全、易用 業界最高的編程性能，節省人力成本 支持脫機燒錄 支持在線編程（ISP） 外形小巧，方便產品現場升級 堅實的烤漆鐵質外殼，更美觀耐用、抗電磁干擾能力強 低功耗（<0.5W），綠色環保
上傳時間： 2013-11-19
上傳用戶：uuuuuuu
winCE msdn講座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上傳時間： 2013-10-31
上傳用戶：jrsoft
針對傳統集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊，在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調的原理和實現方法，推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-06
上傳用戶：liu123
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV set, the stereo, the VCR, and the satellite receiver.
上傳時間： 2013-11-13
上傳用戶：頂得柱
針對傳統集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊，在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調的原理和實現方法，推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-19
上傳用戶：neu_liyan
本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中。 關鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上傳時間： 2013-11-10
上傳用戶：hz07104032
tty驅動 * This driver shows how to create a minimal tty driver. It does not rely on * any backing hardware, but creates a timer that emulates data being received * from some kind of hardware.
標簽： driver tty backing minimal
上傳時間： 2013-12-04
上傳用戶：金宜
One of the most important issues affecting the implementation of microcontroller software deals with the data-decision algorithm. Data-decision refers to decoding the DIO-pin from the CC400/CC900. Two main principles exist for decoding Manchester-coded data: Data decision based on timing the period between transitions, and data decision based on oversampling.
標簽： microcontroller implementation important affecting
上傳時間： 2013-12-18
上傳用戶：671145514
