在汽車發動機起動時，若發動機起動后起動機不能及時斷電，將會燒毀起動機或損壞飛輪齒環；若變速器不在空檔位置起動，則起動機的瞬間動力將使汽車位移，還可能引起交通事故和人身安全。為此介紹一種利用NXP P89LPC901單片機控制的汽車起動保護控制器，通過檢測汽車起動開關、變速箱檔位、發動機轉速，實現對汽車發動機起動過程檢測和保護。起動保護控制器在發動機起動過程中通過采用逐個關閉打開負載系統，解決汽車發動機過程中因起動電流大而對汽車電源的沖擊影響,延長了電瓶壽命。
Abstract:
When the automotive engine is started, the engine start motor and flywheel gear may be damaged， even traffic accidents and personal safeties may be caused by wrong operation or other factors.In order to ensure the automotive engine can be started normally and safely,it is necessary that the protecting measures and methods are considered in the automotive electrical control system.This paper introduces a kind of the automotive engine starting protect controller based on NXP P89LPC901 MCU.The controller can protect the engine starting process by detecting the starter key switch,transmission stall and engine speed.Through the use of close and open load system,the controller can solve the impact on automotive power because of the high-current load in the process of the automobile engine starting, and extend battery life.
針對當前安檢力學試驗機所能完成的試驗種類單一、自動化程度低等問題，提出一種以ATmega128單片機為核心控制器的安檢力學試驗機的設計。詳細闡述了該安檢力學試驗機各個組成部分的設計原理和方案，并且給出了各部分的軟件設計思想和操作流程。經過大量測試試驗表明：設計的安檢力學試驗機可以完成多達十余種的力學安檢試驗，完全符合相關國家標準，并且具有數據采集精度高、傳輸速度快、操作安全簡便等特點，實現了安檢設備的多功能化、數字化和自動化。
Abstract:
Currently， many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems， a new kind of mechanical security testing machine， using ATmega128 micro-controller as its core controller， has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail， and the software architecture and the operation processes of each part are given. After having done many testing， we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general， this machine is a multi-functional， highly automatic， digitalized security testing device.
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable across platforms and network types
NTL is a high-performance, portable C++ library providing data structures and algorithms for manipulating signed, arbitrary length integers, and for vectors, matrices, and polynomials over the integers and over finite fields.
SR-tree is an index structure for high-dimensional nearest neighbor queries，C++ sourcecode. SR-tree outperforms the R*-tree and the SS-tree especially for high-dimensional and non-uniform data which are likely to appear in the actual image / video applications.
