FPGA-based high-order FIR filter design
標(biāo)簽： FPGA-based high-order filter design
上傳時(shí)間： 2013-12-02
上傳用戶(hù)：ommshaggar
The decision of a boundary problem for the differential equation of the second order a method of iterations
標(biāo)簽： differential the decision boundary
上傳時(shí)間： 2013-12-02
上傳用戶(hù)：lx9076
完整的原創(chuàng)單片機(jī)控制彩色液晶源代碼（keil工程） 320x240液晶模塊底層驅(qū)動(dòng) 控制芯片5408 CPU LPC2131(or Higher) 開(kāi)發(fā)環(huán)境 keil C for ARM (MDK3.01) 65536色顯示 支持16*16 12*12字庫(kù) 支持圖形 支持觸摸 所以程序模塊化設(shè)計(jì)便于移植
標(biāo)簽： keil 320x240 Higher 2131
上傳時(shí)間： 2017-08-12
上傳用戶(hù)：偷心的海盜
This book bridges the gap between higher abstract modeling concepts and the lower-level programming aspects of embedded systems development. You gain a solid understanding of real-time embedded systems with detailed examples and industry wisdom.
標(biāo)簽： lower-level programming the abstract
上傳時(shí)間： 2014-01-14
上傳用戶(hù)：yy541071797
First end second order sigma-delta ADC Simulink model.
標(biāo)簽： sigma-delta Simulink second First
上傳時(shí)間： 2014-01-03
上傳用戶(hù)：啊颯颯大師的
synopsys for the students in order to guide them
標(biāo)簽： synopsys students guide order
上傳時(shí)間： 2017-08-24
上傳用戶(hù)：yangbo69
synopsys for the students in order to guide them
標(biāo)簽： synopsys students guide order
上傳時(shí)間： 2017-08-24
上傳用戶(hù)：杜瑩12345
Improved EMD Using Doubly-Iterative Sifting and High Order Spline Interpolation
標(biāo)簽： Doubly-Iterative Interpolation Improved Sifting
上傳時(shí)間： 2017-08-26
上傳用戶(hù)：zhliu007
This is a simple program in order to test inertia cube harware.
標(biāo)簽： harware inertia program simple
上傳時(shí)間： 2013-12-23
上傳用戶(hù)：ouyangtongze
為了提高超高頻RFID系統(tǒng)中閱讀器在低信噪比的情況下仍具有較高的識(shí)別能力,提出一種基于FPGA系統(tǒng)結(jié)合軟件無(wú)線(xiàn)電方法實(shí)現(xiàn)超高頻RFID射頻前端電路方案。超高頻射頻識(shí)別系統(tǒng)必須符合EPC Class 1generation 2標(biāo)準(zhǔn),所設(shè)計(jì)的電路系統(tǒng)以Xilinx公司的XC6SLX16-2CSG324FPGA芯片為硬件基礎(chǔ),將數(shù)字基帶調(diào)制解調(diào)和中頻濾波電路在FPGA系統(tǒng)中設(shè)計(jì)實(shí)現(xiàn),重點(diǎn)闡述了射頻前端電路的設(shè)計(jì)結(jié)構(gòu)、AD/DA轉(zhuǎn)換電路,以及數(shù)字濾波器的設(shè)計(jì)。實(shí)驗(yàn)結(jié)果表明,所設(shè)計(jì)的超高頻RFID閱讀器簡(jiǎn)化了前端電路系統(tǒng)結(jié)構(gòu),提升了穩(wěn)定性,增強(qiáng)了抗干擾能力。該電路系統(tǒng)在信噪比較低的情況下,能夠較好地實(shí)現(xiàn)915MHz頻率的射頻接收和發(fā)送。In order to improve the reader UHF RFID system still has a higher ability to identify,in the case of low signal-to-noise ratio.The UHF RFID systems must comply with EPC Class 1 generation 2 standard.In this paper,the design of the circuit system based on Xilinx＇s XC6SLX16-2CSG324 FPGA chip,and presents UHF RFID RF front-end circuit with software radio based on FPGA system.Digital baseband modem and IF filter circuit is designed and implemented in the FPGA system,and focused on designing the structure of the RF front-end circuit,AD/DA conversion circuits,and digital filter.Experimental results show that the UHF RFID reader de...
標(biāo)簽： 915mhz 超高頻 rfid 閱讀 射頻 前端 電路 設(shè)計(jì)
上傳時(shí)間： 2022-04-17
上傳用戶(hù)：shjgzh
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