面向Eclips的Nios II軟件構建工具手冊 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時間： 2013-11-02
上傳用戶：瓦力瓦力hong
怎樣使用Nios II處理器來構建多處理器系統 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上傳時間： 2013-11-21
上傳用戶：lo25643
使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時間： 2013-10-13
上傳用戶：黃婷婷思密達
Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上傳時間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
上傳時間： 2015-01-01
上傳用戶：mahone
Nios II內核詳細實現
上傳時間： 2015-01-01
上傳用戶：源碼3
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標簽： CoolRunner-II XAPP CPLD 380
上傳時間： 2013-10-26
上傳用戶：kiklkook
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標簽： CoolRunner-II Xilinx XAPP CPLD
上傳時間： 2013-12-16
上傳用戶：qwer0574
東南大學綜合電子實踐Quartus ii課程設計報告 包含跑馬燈，數字鐘和交通燈設計
上傳時間： 2015-01-02
上傳用戶：超凡大師
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