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INclude

INclude是一個(gè)計(jì)算機(jī)專業(yè)術(shù)語(yǔ),一指C/C++中包含頭文件命令,用于將指定頭文件嵌入源文件中。二指INclude指令,在JSP中包含一個(gè)靜態(tài)的文件,同時(shí)解析這個(gè)文件中的JSP語(yǔ)句。三指PHP語(yǔ)句。
  • 將您的微控制器ADC升級(jí)至真正的12位性能

      Many 8-bit and 16-bit microcontrollers feature 10-bitinternal ADCs. A few INclude 12-bit ADCs, but these oftenhave poor or nonexistent AC specifi cations, and certainlylack the performance to meet the needs of an increasingnumber of applications. The LTC®2366 and its slowerspeed versions offer a high performance alternative, asshown in the AC specifi cations in Table 1. Compare theseguaranteed specifi cations with the ADC built into yourcurrent microcontroller.

    標(biāo)簽: ADC 微控制器 性能

    上傳時(shí)間: 2013-10-26

    上傳用戶:jackandlee

  • 數(shù)據(jù)采集電路分析

      This application note features 8-, 10-, and 12-bit dataacquisition components in various circuit configurations.The circuits INclude battery monitoring, temperature sensing,isolated serial interfaces, and microprocessor andmicrocontroller serial and parallel interfaces. Also INcludedare voltage reference circuits (Application Note 42contains more voltage reference circuits).

    標(biāo)簽: 數(shù)據(jù)采集 電路分析

    上傳時(shí)間: 2014-01-15

    上傳用戶:zq70996813

  • ADC轉(zhuǎn)換器技術(shù)用語(yǔ) (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not INclude acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    標(biāo)簽: Converter Defi ADC 轉(zhuǎn)換器

    上傳時(shí)間: 2013-11-12

    上傳用戶:pans0ul

  • 為您的FPGA選擇合適的電源

    Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These INclude (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.

    標(biāo)簽: FPGA 電源

    上傳時(shí)間: 2013-11-12

    上傳用戶:金苑科技

  • DN443 2.2V降壓型同步控制器

      Many telecommunications and computing applicationsneed high effi ciency step-down DC/DC converters thatcan operate from a very low input voltage. The highoutput power synchronous controller LT3740 is idealfor these applications, converting input supplies rangingfrom 2.2V to 22V to outputs as low as 0.8V with loadcurrents from 2A to 20A. Applications INclude distributedpower systems, point-of-load regulation and conversionof logic supplies.

    標(biāo)簽: 443 2.2 DN 降壓型

    上傳時(shí)間: 2013-11-05

    上傳用戶:zhf01y

  • 如何制作使用μModule降壓穩(wěn)壓器的輸入輸出電壓

      Linear Technology’s DC/DC step-down μModule®regulators are complete switchmode power supplies in asurface-mount package. They INclude the DC/DC controller,inductor, power switches and supporting circuitry.These highly integrated regulators also provide an easysolution for applications that require negative outputvoltages. In other words, these products can operate asinverting buck-boost regulators. As a result, the lowestpotential in the circuit is not the standard 0V, but –VOUT,which must be tied to the μModule regulator’s GND. Allsignals are now referred to –VOUT.

    標(biāo)簽: Module 如何制作 降壓穩(wěn)壓器 輸入輸出

    上傳時(shí)間: 2013-10-22

    上傳用戶:ztj182002

  • Designing Linear Circuits for 5V Operation

      In predominantly digital systems it is often necessaryto INclude linear circuit functions. Traditionally, separatepower supplies have been used to run the linear components(see Box, “Linear Power Supplies—Past, Present,and Future”).

    標(biāo)簽: Designing Operation Circuits Linear

    上傳時(shí)間: 2013-11-04

    上傳用戶:sdq_123

  • 用鍵盤(pán)控制的LED燈

    #INclude<reg51.h>

    標(biāo)簽: LED 鍵盤(pán)控制

    上傳時(shí)間: 2013-11-01

    上傳用戶:liujinzhao

  • TLC2543 中文資料

    TLC2543是TI公司的12位串行模數(shù)轉(zhuǎn)換器,使用開(kāi)關(guān)電容逐次逼近技術(shù)完成A/D轉(zhuǎn)換過(guò)程。由于是串行輸入結(jié)構(gòu),能夠節(jié)省51系列單片機(jī)I/O資源;且價(jià)格適中,分辨率較高,因此在儀器儀表中有較為廣泛的應(yīng)用。 TLC2543的特點(diǎn) (1)12位分辯率A/D轉(zhuǎn)換器; (2)在工作溫度范圍內(nèi)10μs轉(zhuǎn)換時(shí)間; (3)11個(gè)模擬輸入通道; (4)3路內(nèi)置自測(cè)試方式; (5)采樣率為66kbps; (6)線性誤差±1LSBmax; (7)有轉(zhuǎn)換結(jié)束輸出EOC; (8)具有單、雙極性輸出; (9)可編程的MSB或LSB前導(dǎo); (10)可編程輸出數(shù)據(jù)長(zhǎng)度。 TLC2543的引腳排列及說(shuō)明    TLC2543有兩種封裝形式:DB、DW或N封裝以及FN封裝,這兩種封裝的引腳排列如圖1,引腳說(shuō)明見(jiàn)表1 TLC2543電路圖和程序欣賞 #INclude<reg52.h> #INclude<intrins.h> #define uchar unsigned char #define uint unsigned int sbit clock=P1^0; sbit d_in=P1^1; sbit d_out=P1^2; sbit _cs=P1^3; uchar a1,b1,c1,d1; float sum,sum1; double  sum_final1; double  sum_final; uchar duan[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f}; uchar wei[]={0xf7,0xfb,0xfd,0xfe};  void delay(unsigned char b)   //50us {           unsigned char a;           for(;b>0;b--)                     for(a=22;a>0;a--); }  void display(uchar a,uchar b,uchar c,uchar d) {    P0=duan[a]|0x80;    P2=wei[0];    delay(5);    P2=0xff;    P0=duan[b];    P2=wei[1];    delay(5);   P2=0xff;   P0=duan[c];   P2=wei[2];   delay(5);   P2=0xff;   P0=duan[d];   P2=wei[3];   delay(5);   P2=0xff;   } uint read(uchar port) {   uchar  i,al=0,ah=0;   unsigned long ad;   clock=0;   _cs=0;   port<<=4;   for(i=0;i<4;i++)  {    d_in=port&0x80;    clock=1;    clock=0;    port<<=1;  }   d_in=0;   for(i=0;i<8;i++)  {    clock=1;    clock=0;  }   _cs=1;   delay(5);   _cs=0;   for(i=0;i<4;i++)  {    clock=1;    ah<<=1;    if(d_out)ah|=0x01;    clock=0; }   for(i=0;i<8;i++)  {    clock=1;    al<<=1;    if(d_out) al|=0x01;    clock=0;  }   _cs=1;   ad=(uint)ah;   ad<<=8;   ad|=al;   return(ad); }  void main()  {   uchar j;   sum=0;sum1=0;   sum_final=0;   sum_final1=0;    while(1)  {              for(j=0;j<128;j++)          {             sum1+=read(1);             display(a1,b1,c1,d1);           }            sum=sum1/128;            sum1=0;            sum_final1=(sum/4095)*5;            sum_final=sum_final1*1000;            a1=(int)sum_final/1000;            b1=(int)sum_final%1000/100;            c1=(int)sum_final%1000%100/10;            d1=(int)sum_final%10;            display(a1,b1,c1,d1);           }         } 

    標(biāo)簽: 2543 TLC

    上傳時(shí)間: 2013-11-19

    上傳用戶:shen1230

  • MEGA16制作的電子時(shí)鐘(附仿真圖+源代碼)

    #INclude <iom16v.h> #INclude <macros.h> #define uchar unsigned char #define uint unsigned int uchar num,miao,fen,shi,miaoge,miaoshi,fenge,fenshi,shig

    標(biāo)簽: MEGA 16 電子時(shí)鐘 仿真圖

    上傳時(shí)間: 2013-10-14

    上傳用戶:sc965382896

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