For developers using FPGAs for the
implementation of floating-point DSP
functions, one key challenge is how to
decompose the computation algorithm
into sequences of parallel hardware
processes while efficiently managing data flow through the parallel pipelines of these processes.
標(biāo)簽：
floating-point
implementation
developers
functions
上傳時(shí)間：
2013-12-16
上傳用戶：tonyshao
