使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23，FPGA/CPLD系統時鐘為24.576MHz
1、AIC系統時鐘為12.288MHz，SPI時鐘為6.144MHz
2、AIC處于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、幀同步在96KHz
c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.
Shortest Paths with Multiplicative Cost. In a given undirected graph, the path cost is measured as a product of all the edges in the path. The weights are rational numbers (e.g., 0.25, 0.75, 3.75 etc) or integers (2, 3). There are no negative edges. Given such a graph as input, you are to output the shortest path between any two given vertices. Input is the adjacency matrix and the two vertices. You must output the path.
In some graphs, the shortest path is given by optimizing two different metrics: the sum of weights of the edges and the number of edges. For example: if two paths with equal cost exist then, the path with the least number of edges is chosen as the shortest path. Given this metric, you have find out the shortest path between a given pair of vertices in the input graph. The output should be the number of edges on the path, the cost of the shortest path, and the path itself. Input is the adjacency matrix and the two vertices.
