Radio Frequency Integrated Circuit Design I enjoyed reading this book for a number of reasons. One reason is that itaddresses high-speed analog design in the context of microwave issues. This isan advanced-level book, which should follow courses in basic circuits andtransmission Lines. Most analog integrated circuit designers in the past workedon applications at low enough frequency that microwave issues did not arise.As a consequence, they were adept at lumped parameter circuits and often notcomfortable with circuits where waves travel in space. However, in order todesign radio frequency (RF) communications integrated circuits (IC) in thegigahertz range, one must deal with transmission Lines at chip interfaces andwhere interconnections on chip are far apart. Also, impedance matching isaddressed, which is a topic that arises most often in microwave circuits. In mycareer, there has been a gap in comprehension between analog low-frequencydesigners and microwave designers. Often, similar issues were dealt with in twodifferent languages. Although this book is more firmly based in lumped-elementanalog circuit design, it is nice to see that microwave knowledge is brought inwhere necessary.Too many analog circuit books in the past have concentrated first on thecircuit side rather than on basic theory behind their application in communications.The circuits usually used have evolved through experience, without asatisfying intellectual theme in describing them. Why a given circuit works bestcan be subtle, and often these circuits are chosen only through experience. Forthis reason, I am happy that the book begins first with topics that require anintellectual approach—noise, linearity and filtering, and technology issues. Iam particularly happy with how linearity is introduced (power series). In therest of the book it is then shown, with specific circuits and numerical examples,how linearity and noise issues arise.
上傳時間： 2014-12-23
上傳用戶：han_zh
第一章 傳輸線理論一 傳輸線原理二 微帶傳輸線三 微帶傳輸線之不連續分析第二章 被動組件之電感設計與分析一 電感原理二 電感結構與分析三 電感設計與模擬四 電感分析與量測傳輸線理論與傳統電路學之最大不同，主要在于組件之尺寸與傳導電波之波長的比值。當組件尺寸遠小于傳輸線之電波波長時，傳統的電路學理論才可以使用，一般以傳輸波長（Guide wavelength）的二十分之ㄧ（λ/20）為最大尺寸，稱為集總組件（Lumped elements）；反之，若組件的尺寸接近傳輸波長，由于組件上不同位置之電壓或電流的大小與相位均可能不相同，因而稱為散布式組件（Distributed elements）。 由于通訊應用的頻率越來越高，相對的傳輸波長也越來越小，要使電路之設計完全由集總組件所構成變得越來越難以實現，因此，運用散布式組件設計電路也成為無法避免的選擇。 當然，科技的進步已經使得集總組件的制作變得越來越小，例如運用半導體制程、高介電材質之低溫共燒陶瓷（LTCC）、微機電（MicroElectroMechanical Systems, MEMS）等技術制作集總組件，然而，其中電路之分析與設計能不乏運用到散布式傳輸線的理論，如微帶線（Microstrip Lines）、夾心帶線（Strip Lines）等的理論。因此，本章以討論散布式傳輸線的理論開始，進而以微帶傳輸線為例介紹其理論與公式，并討論微帶傳輸線之各種不連續之電路，以作為后續章節之被動組件的運用。
標簽： 傳輸線
上傳時間： 2014-01-10
上傳用戶：sunshie
Calculation of the Differential Impedance of Tracks on FR4 substrates There is a discrepancy between calculated and measured values of impedance for differential transmission Lineson FR4. This is especially noticeable in the case of surface microstrip configurations. The anomaly is shown tobe due to the nature of the substrate material. This needs to be considered as a layered structure of epoxy resinand glass fibre. Calculations, using Boundary Element field methods, show that the distribution of the electricfield within this layered structure determines the apparent dielectric constant and therefore affects theimpedance. Thus FR4 cannot be considered to be uniform dielectric when calculating differential impedance.
上傳時間： 2014-12-24
上傳用戶：DE2542
What would happen if someone connected 24V to your12V circuits? If the power and ground Lines were inadvertentlyreversed, would the circuits survive? Does yourapplication reside in a harsh environment, where the inputsupply can ring very high or even below ground? Evenif these events are unlikely, it only takes one to destroya circuit board.
上傳時間： 2013-10-26
上傳用戶：jackandlee
單片機作為一種微型計算機，其內部具有一定的存儲單元（8031除外），但由于其內部存儲單元及端口有限，很多情況下難以滿足實際需求。為此介紹一種新的擴展方法，將數據線與地址線合并使用，通過軟件控制的方法實現數據線與地址線功能的分時轉換，數據線不僅用于傳送數據信號，還可作為地址線、控制線，用于傳送地址信號和控制信號，從而實現單片機與存儲器件的有效連接。以單片機片外256KB數據存儲空間的擴展為例，通過該擴展方法，僅用10個I/O端口便可實現，與傳統的擴展方法相比，可節約8個I/O端口。 Abstract: As a micro-computer,the SCM internal memory has a certain units(except8031),but because of its internal storage units and the ports are limited,in many cases it can not meet the actual demand.So we introduced a new extension method,the data line and address Lines combined through software-controlled approach to realize the time-conversion functions of data Lines and address Lines,so the data Lines not only transmited data signals,but also served as address Lines and control Lines to transmit address signals and control signals,in order to achieve an effective connection of microcontroller and memory chips.Take microcontroller chip with256KB of data storage space expansion as example,through this extension method,with only10I/O ports it was achieved,compared with the traditional extension methods,this method saves8I/O ports.
上傳時間： 2014-12-26
上傳用戶：adada
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 Lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
上傳時間： 2013-11-08
上傳用戶：laozhanshi111
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission Lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上傳時間： 2013-10-13
上傳用戶：ytulpx
The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) Lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
上傳時間： 2013-11-15
上傳用戶：fklinran
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) Lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上傳時間： 2013-11-21
上傳用戶：q123321
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) Lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
