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Loss-Tolerant

  • 優(yōu)化輸電線路 精確測量電壓駐波比(VSWR)

    Abstract: Impedance mismatches in a radio-frequency (RF) electrical transmission line cause power loss andreflected energy. Voltage standing wave ratio (VSWR) is a way to measure transmission line imperfections. Thistutorial defines VSWR and explains how it is calculated. Finally, an antenna VSWR monitoring system is shown.

    標(biāo)簽: VSWR 輸電線路 精確測量 電壓駐波比

    上傳時間: 2013-10-19

    上傳用戶:yuanwenjiao

  • 一種改進的簡單的電纜仿真模型

    Abstract: Nonideal cable dispersive effects can affect system performance. This application note discusses the twomain loss effects related to cables (skin-effect and dielectric losses), and presents a simple method of modeling thecable for use in standard SPICE simulators.

    標(biāo)簽: 電纜仿真 模型

    上傳時間: 2014-11-18

    上傳用戶:wxnumen

  • 無需檢測電阻的小型DFN封裝電路斷路器

      Traditionally, an Electronic Circuit Breaker (ECB) comprisesa MOSFET, a MOSFET controller and a current senseresistor. The LTC®4213 does away with the sense resistorby using the RDS(ON) of the external MOSFET. The resultis a simple, small solution that offers a signifi cant lowinsertion loss advantage at low operating load voltage.The LTC4213 features two circuit breaking responses tovarying overload conditions with three selectable tripthresholds and a high side drive for an external N-channelMOSFET switch.

    標(biāo)簽: DFN 檢測電阻 封裝 電路斷路器

    上傳時間: 2014-03-02

    上傳用戶:lixinxiang

  • 雪崩光電二極管的偏置電壓和電流檢測電路

      Avalanche photodiodes (APDs) are widely utilized in laserbased fiberoptic systems to convert optical data intoelectrical form. The APD is usually packaged with a signalconditioning amplifier in a small module. An APD receivermodule and attendant circuitry appears in Figure 1. TheAPD module (figure right) contains the APD and a transimpedance(e.g., current-to-voltage) amplifier. An opticalport permits interfacing fiberoptic cable to the APD’sphotosensitive portion. The module’s compact constructionfacilitates a direct, low loss connection between theAPD and the amplifier, necessary because of the extremelyhigh speed data rates involved

    標(biāo)簽: 雪崩 光電二極管 偏置電壓 電流檢測電路

    上傳時間: 2013-10-25

    上傳用戶:brain kung

  • C8051F020

    HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C

    標(biāo)簽: C8051F020

    上傳時間: 2013-10-12

    上傳用戶:lalalal

  • lpc2478完全使用手冊

    NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.

    標(biāo)簽: 2478 lpc 使用手冊

    上傳時間: 2013-11-15

    上傳用戶:zouxinwang

  • PCA9517 Level translating I2C-

    The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.

    標(biāo)簽: translating Level 9517 PCA

    上傳時間: 2013-12-25

    上傳用戶:wsf950131

  • PCA9519 4channel level transla

    The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.

    標(biāo)簽: 4channel transla level 9519

    上傳時間: 2013-11-19

    上傳用戶:jisiwole

  • 容遲網(wǎng)絡(luò)中基于復(fù)制策略的單播路由算法研究

    容遲/容延網(wǎng)絡(luò)(Delay Tolerant Network/DTN)泛指由于節(jié)點移動、能量管理、調(diào)度等原因而出現(xiàn)頻繁中斷、甚至長時間處于中斷狀態(tài)的一類網(wǎng)絡(luò)。針對DTN具有的時延高、割裂頻繁、節(jié)點能量受限、以及節(jié)點移動性等特點,通過對DTN中基于復(fù)制策略的單播路由策略進行分類和比較,提出了如何優(yōu)化DTN單播路由算法、提高網(wǎng)絡(luò)傳輸率的建議。

    標(biāo)簽: 容遲網(wǎng)絡(luò) 策略 路由 算法研究

    上傳時間: 2013-11-24

    上傳用戶:xiaojie

  • lpc2292/lpc2294 pdf datasheet

    The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.

    標(biāo)簽: lpc datasheet 2292 2294

    上傳時間: 2014-12-30

    上傳用戶:aysyzxzm

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