針對使用硬件描述語言進行設(shè)計存在的問題，提出一種基于FPGA并采用DSP Builder作為設(shè)計工具的數(shù)字信號處理器設(shè)計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計流程，設(shè)計了一個12階FIR 低通數(shù)字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設(shè)計進行了驗證。結(jié)果表明，所設(shè)計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標簽： Builder FPGA DSP 數(shù)字信號處理器
上傳時間： 2013-11-17
上傳用戶：lo25643
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時間： 2013-11-10
上傳用戶：XLHrest
HDB3(High Density Bipolar三階高密度雙極性)碼是在AMI碼的基礎(chǔ)上改進的一種雙極性歸零碼，它除具有AMI碼功率譜中無直流分量，可進行差錯自檢等優(yōu)點外，還克服了AMI碼當信息中出現(xiàn)連“0”碼時定時提取困難的缺點，而且HDB3碼頻譜能量主要集中在基波頻率以下，占用頻帶較窄，是ITU-TG.703推薦的PCM基群、二次群和三次群的數(shù)字傳輸接口碼型,因此HDB3碼的編解碼就顯得極為重要了[1]。目前，HDB3碼主要由專用集成電路及相應(yīng)匹配的外圍中小規(guī)模集成芯片來實現(xiàn)，但集成程度不高，特別是位同步提取非常復(fù)雜，不易實現(xiàn)。隨著可編程器件的發(fā)展，這一難題得到了很好地解決。
上傳時間： 2013-11-21
上傳用戶：sy_jiadeyi
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-05
上傳用戶：a6697238
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2014-08-16
上傳用戶：adada
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時間： 2014-12-28
上傳用戶：zhang97080564
WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間： 2013-10-22
上傳用戶：685
波長信號的解調(diào)是實現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設(shè)計，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時間： 2014-07-24
上傳用戶：caiguoqing
在車載自組網(wǎng)中，路由協(xié)議很大程度上決定了整個網(wǎng)絡(luò)的性能。如何有效的利用車流信息提高傳輸質(zhì)量是改善路由性能的一個關(guān)鍵問題。本文基于速度-密度線性模型，提出了一種實時車流密度的路由協(xié)議RVDR（Real-time Vehicle Density Routing）。該協(xié)議通過與鄰居節(jié)點交換的速度信息，對相關(guān)道路車流密度進行預(yù)測，并給出基于車流密度信息的路徑選擇方法。仿真結(jié)果表明，與現(xiàn)有協(xié)議相比，RVDR協(xié)議在實時性和高效性等性能方面得到改進。
上傳時間： 2014-07-10
上傳用戶：ZJX5201314
CC2540 軟件開發(fā)手冊
標簽： Bluetooth Developer Software Energy
上傳時間： 2013-10-11
上傳用戶：xzt
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