用fpga實現(xiàn)的DA轉(zhuǎn)換器，有說明和源碼，VDHL文件。\\r\\nA PLD Based Delta-Sigma DAC\\r\\nDelta-Sigma modulation is the simple, yet powerful,\\r\\ntechnique responsible for the extraordinary\\r\\nperformance and low cost of today s audio CD\\r\\nplayers. The simplest Delta-Sigm
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
為了滿足現(xiàn)代高速通信中頻率快速轉(zhuǎn)換的需求，基于坐標(biāo)旋轉(zhuǎn)數(shù)字計算（CORDIC，Coordinate Rotation Digital Computer）算法完成正交直接數(shù)字頻率合成（ODDFS，Orthogonal Direct Digital Frequency Synthesizer）電路設(shè)計方案。采用MATLAB和Xilinx System Generator開發(fā)工具搭建電路的系統(tǒng)模型，通過現(xiàn)場可編程門陣列（FPGA，F(xiàn)ield Programmable Gate Array）完成電路的寄存器傳輸級（RTL，Register Transfer Level）驗證，仿真結(jié)果表明電路設(shè)計具有很高的有效性和可行性。
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
