This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
標(biāo)簽： applications development hardware paper
上傳時間： 2013-12-21
上傳用戶：jichenxi0730
It was proposed that perfect invisibility cloaks can be constructed for hiding objects from electromagnetic illumination (Pendry et al., Science 312, p. 1780). The cylindrical cloaks experimentally demonstrated (Schurig et al., Science 314, p. 997) and theoretically proposed (Cai et al., Nat. Photon. 1, p. 224) have however simplified material parameters in order to facilitate easier realization as well as to avoid infinities in optical constants. Here we show that the cylindrical cloaks with simplified material parameters inherently allow the zeroth-order cylindrical wave to pass through the cloak as if the cloak is made of a homogeneous isotropic medium, and thus visible. To all high-order cylindrical waves, our numerical simulation suggests that the simplified cloak inherits some properties of the ideal cloak, but finite scatterings exist.
標(biāo)簽： invisibility constructed proposed electrom
上傳時間： 2013-12-18
上傳用戶：13215175592
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device鈥檚 cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
標(biāo)簽： electrically programmable provides erasable
上傳時間： 2017-04-09
上傳用戶：cc1015285075
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 128-byte page programming function to make their write operation faster. Note: Renesas Technology鈥檚 serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology鈥檚 sales office before using industrial applications such as automotive systems, embedded controllers, and meters
標(biāo)簽： Electrically Programmable interface Erasable
上傳時間： 2014-01-07
上傳用戶：xiaohuanhuan
Airline Reservations System A small airline has just purchased a computer for its new automated reservation system. You have been asked to develop the new system called ARSystem. You are to write an application to assign seats on each flight of the airline s only plane (capacity: 24 seats.) Your application should display the following alternatives: Please type 1 for FirstClass and Please type 2 for Economy. If the user types 1, your application should assign a seat in the first-class section (seats 1-8). If the user types 2, your application should assign a seat in the economy section (seats 9-24). Your application should then display a boarding pass indicating the person s seat number and whether it is in the first-class or economy
標(biāo)簽： Reservations automated purchased computer
上傳時間： 2017-04-14
上傳用戶：lizhizheng88
You will recieve a Standard Grade for completion of this Extra credit will be given for a more creative approach to the problem, either minimum amount of code, an additional display of seating beyond just the boarding pass, etc
標(biāo)簽： will completion for Standard
上傳時間： 2014-01-02
上傳用戶：dongqiangqiang
Face Recognition Library ======================== Advanced face recognition DLL using two functions : Train and Recognize. Uses neural net back propogation alogorithm with more AI tools added for imaging optimization. Library works great even for a low resolution web cam image and requires the user to align to a mirror frame on screen. Complete Source Code with Video capture and feature extraction kit for Registered Users. Please register here for only $299 with Source Code : http://www.research-lab.com/facerecognitionorder.htm (c) www.research-lab.com
標(biāo)簽： Recognition recognition Advanced Library
上傳時間： 2017-04-25
上傳用戶：784533221
This software allows users to see how a serial async com port can be used to comunicate with a sync device (SPI). In this case, the software reads a low cost digital temperature sensor IC.
標(biāo)簽： comunicate software allows serial
上傳時間： 2014-01-16
上傳用戶：huangld
The BuildBot is a system to automate the compile/test cycle required by most software projects. CVS commits trigger new builds, run on a variety of client machines. Build status (pass/fail/etc) are displayed on a web page or through other protocols.
標(biāo)簽： BuildBot automate required projects
上傳時間： 2017-05-06
上傳用戶：懶龍1988
This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.
標(biāo)簽： errorcorrecting architecture efficient devoted
上傳時間： 2017-05-08
上傳用戶：康郎
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