verilog
標(biāo)簽： Verilog HDL 程序設(shè)計 教程
上傳時間： 2013-10-26
上傳用戶：linlin
關(guān)于Verilog中的可綜合語句和不可綜合語句的匯總介紹
標(biāo)簽： verilog
上傳時間： 2013-11-27
上傳用戶：squershop
Verilog經(jīng)典教程
上傳時間： 2013-10-31
上傳用戶：waitingfy
宇聞著Verilog數(shù)字系統(tǒng)設(shè)計教程word版
標(biāo)簽： Verilog word 數(shù)字系統(tǒng) 設(shè)計教程
上傳時間： 2013-11-03
上傳用戶：zhang_yi
宇聞著Verilog數(shù)字系統(tǒng)設(shè)計教程word版
標(biāo)簽： Verilog word 數(shù)字系統(tǒng) 設(shè)計教程
上傳時間： 2013-10-11
上傳用戶：angle
《Verilog HDL程序設(shè)計與實踐》系統(tǒng)講解了Verilog HDL的基本語法和高級應(yīng)用技巧，對于每個知識點都按照開門見山、自頂向下的方式來組織內(nèi)容，在介紹相關(guān)知識點之前，先告訴讀者其出現(xiàn)的背景、本質(zhì)特征以及應(yīng)用場景，讓讀者不僅掌握基本語法，還能夠獲得深層次理解。從結(jié)構(gòu)上講，《Verilog HDL程序設(shè)計與實踐》以Verilog HDL的各方面開發(fā)為主線，遵照硬件應(yīng)用系統(tǒng)開發(fā)的基本步驟和思路進行詳細(xì)講解，并穿插介紹ISE開發(fā)工具的操作技巧與注意事項，具備很強的可讀性、指導(dǎo)性和實用性。
標(biāo)簽： Verilog HDL 程序設(shè)計
上傳時間： 2013-11-21
上傳用戶：silenthink
夏宇聞Verilog經(jīng)典教程
上傳時間： 2013-10-21
上傳用戶：zhangyi99104144
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
標(biāo)簽： Verilog XAPP CPLD 143
上傳時間： 2013-11-11
上傳用戶：y13567890
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上傳時間： 2013-11-01
上傳用戶：xzt
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-23
上傳用戶：我干你啊
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