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MULTIPLICATION

  • Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time d

    Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time domain is the effectively the same as element-by-element MULTIPLICATION in the frequency domain.

    標(biāo)簽： equal-length Convolution convolution Highlights

    上傳時(shí)間： 2014-01-22

    上傳用戶：aig85

  • Mapack可用來做矩陣運(yùn)算 Mapack is a .NET class library for basic linear algebra computations. It supports th

    Mapack可用來做矩陣運(yùn)算 Mapack is a .NET class library for basic linear algebra computations. It supports the following matrix operations and properties: MULTIPLICATION, Addition, Subtraction, Determinant, Norm1, Norm2, Frobenius Norm, Infinity Norm, Rank, Condition, Trace, Cholesky, LU, QR, Single Value decomposition, Least Squares solver, Eigenproblem solver, Equation System solver. The algorithms were adapted from Mapack for COM, Lapack and the Java Matrix Package.

    標(biāo)簽： Mapack computations supports algebra

    上傳時(shí)間： 2017-01-26

    上傳用戶：tb_6877751

  • this code is a implementation of the Discrete cosinuss transformation. In this code I have used the

    this code is a implementation of the Discrete cosinuss transformation. In this code I have used the direct méthode of calcul by used the equation without used the maatrix MULTIPLICATION.

    標(biāo)簽： this code implementation transformation

    上傳時(shí)間： 2013-12-19

    上傳用戶：lanwei

  • 基于FPGA設(shè)計(jì)的相關(guān)論文資料大全 84篇

    基于FPGA設(shè)計(jì)的相關(guān)論文資料大全 84篇用FPGA實(shí)現(xiàn)FFT的研究 劉朝暉　　韓月秋 摘　要　目的　針對(duì)高速數(shù)字信號(hào)處理的要求，給出了用現(xiàn)場(chǎng)可編程門陣列(FPGA)實(shí)現(xiàn)的 快速傅里葉變換(FFT)方案.方法　算法為按時(shí)間抽取的基4算法，采用遞歸結(jié)構(gòu)的塊浮點(diǎn)運(yùn) 算方案，蝶算過程只擴(kuò)展兩個(gè)符號(hào)位以適應(yīng)雷達(dá)信號(hào)處理的特點(diǎn)，乘法器由陣列乘法器實(shí) 現(xiàn).結(jié)果　采用流水方式保證系統(tǒng)的速度，使取數(shù)據(jù)、計(jì)算旋轉(zhuǎn)因子、復(fù)乘、DFT等操作協(xié) 調(diào)一致，在計(jì)算、通信和存儲(chǔ)間取得平衡，避免了瓶頸的出現(xiàn).結(jié)論　實(shí)驗(yàn)表明，用FPGA 實(shí)現(xiàn)高速數(shù)字信號(hào)處理的算法是一個(gè)可行的方案. 關(guān)鍵詞　離散傅里葉變換； 快速傅里葉變換； 塊浮點(diǎn)運(yùn)算； 可編程門陣列 分類號(hào)　TP39； TN957.511 Implementation of FFT with FPGA Technology Liu Zhaohui　　Han Yueqiu (Department of Electronics Engineering, Beijing Institute of Technology, Beijing　100081) Abstract　Aim　To propose a scheme for implementing FFT with FPGA in accor-dance with the requirement for high speed digital signal processing. Methods　The structure of FPGA and requirement of system were considered in the experiment, radix-4 algorithm of DIT and recursive structure were adopted. The group float point arithmetic operation was used in the butterfly and the array multiplier was used to realize MULTIPLICATION. Results　The pipeline pattern was used to ensure the system speed, it made fetching data, calculating twiddle factor, complex MULTIPLICATION and D

    標(biāo)簽： fpga

    上傳時(shí)間： 2022-03-23

    上傳用戶：

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