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MacHINe-independent

  • Java technology has evolved from a programming language designed to create MacHINe-independent embe

    Java technology has evolved from a programming language designed to create MacHINe-independent embedded systems into a robust, vendor-independent, MacHINe-independent, server-side technology, enabling the corporate community to realize the full potential of web-centric applications. Java began with the release of the Java Development Kit (JDK). It was obv

    標(biāo)簽: MacHINe-independent programming technology designed

    上傳時(shí)間: 2013-12-28

    上傳用戶:lacsx

  • State Machine Coding Styles for Synthesis

      本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn),Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

    標(biāo)簽: Synthesis Machine Coding Styles

    上傳時(shí)間: 2013-10-15

    上傳用戶:dancnc

  • Design Safe Verilog State Machine(Synplicity)

      One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

    標(biāo)簽: Synplicity Machine Verilog Design

    上傳時(shí)間: 2013-10-23

    上傳用戶:司令部正軍級(jí)

  • 基于FPGA+DSP模式的智能相機(jī)設(shè)計(jì)

    針對(duì)嵌入式機(jī)器視覺(jué)系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求,介紹了一種嵌入式視覺(jué)系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析,對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀,提出基于FPGA+DSP模式的硬件平臺(tái),并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明,該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行,完成圖像獲取與分析,并作出相應(yīng)輸出。 Abstract:  This paper introduced an embedded vision system-intelligent camera ,which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture, component modules and image acquisition, transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad, the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design, the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

    標(biāo)簽: FPGA DSP 模式 智能相機(jī)

    上傳時(shí)間: 2013-10-24

    上傳用戶:bvdragon

  • State Machine Coding Styles for Synthesis

      本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn),Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

    標(biāo)簽: Synthesis Machine Coding Styles

    上傳時(shí)間: 2013-10-12

    上傳用戶:sardinescn

  • Design Safe Verilog State Machine(Synplicity)

      One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

    標(biāo)簽: Synplicity Machine Verilog Design

    上傳時(shí)間: 2013-10-20

    上傳用戶:蒼山觀海

  • 基于FPGA+DSP模式的智能相機(jī)設(shè)計(jì)

    針對(duì)嵌入式機(jī)器視覺(jué)系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求,介紹了一種嵌入式視覺(jué)系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析,對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀,提出基于FPGA+DSP模式的硬件平臺(tái),并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明,該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行,完成圖像獲取與分析,并作出相應(yīng)輸出。 Abstract:  This paper introduced an embedded vision system-intelligent camera ,which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture, component modules and image acquisition, transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad, the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design, the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

    標(biāo)簽: FPGA DSP 模式 智能相機(jī)

    上傳時(shí)間: 2013-11-14

    上傳用戶:無(wú)聊來(lái)刷下

  • Boltzmann Machine Optimization 人工智能人工神經(jīng)網(wǎng)絡(luò)源碼

    Boltzmann Machine Optimization 人工智能人工神經(jīng)網(wǎng)絡(luò)源碼

    標(biāo)簽: Optimization Boltzmann Machine 人工智能

    上傳時(shí)間: 2014-12-07

    上傳用戶:努力努力再努力

  • libpcap is a system-independent interface for user-level packet capture. libpcap provides a portable

    libpcap is a system-independent interface for user-level packet capture. libpcap provides a portable framework for low-level network monitoring. Applications include network statistics collection, security monitoring, network debugging, etc.

    標(biāo)簽: libpcap system-independent user-level interface

    上傳時(shí)間: 2014-08-11

    上傳用戶:saharawalker

  • Tiny Machine的源碼

    Tiny Machine的源碼,一個(gè)簡(jiǎn)單易學(xué)習(xí)的

    標(biāo)簽: Machine Tiny 源碼

    上傳時(shí)間: 2015-01-21

    上傳用戶:D&L37

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