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The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash Memory. A 128-bit wide Memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external Memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽：
lpc
datasheet
2292
2294
上傳時(shí)間：
2014-12-30
上傳用戶：aysyzxzm
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data Memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external Memory controller, and multiple digital andanalog peripherals.
標(biāo)簽：
Cortex-M
1850
LPC
內(nèi)核微控制器
上傳時(shí)間：
2014-12-31
上傳用戶：zhuoying119
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of dataMemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external Memory controller, and multiple digital and analog peripherals
標(biāo)簽：
4300
LPC
ARM
雙核微控制器
上傳時(shí)間：
2013-10-28
上傳用戶：15501536189
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On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash Memory.
標(biāo)簽：
1300
LPC
勘誤
數(shù)據(jù)手冊(cè)
上傳時(shí)間：
2013-12-13
上傳用戶：lmq0059
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Today in many applications such as network switches, routers, multi-computers,and processor-Memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽：
時(shí)鐘恢復(fù)
英文
上傳時(shí)間：
2013-10-30
上傳用戶：ysjing
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MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽：
MAXQUSBJTAGOW
評(píng)估板
軟件
上傳時(shí)間：
2013-10-24
上傳用戶：teddysha
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MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽：
MAXQUSBJTAGOW
評(píng)估板
軟件
上傳時(shí)間：
2013-11-23
上傳用戶：truth12
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怎樣使用Nios II處理器來(lái)構(gòu)建多處理器系統(tǒng)
Chapter 1. Creating Multiprocessor Nios II Systems
Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1
Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2
Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3
Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3
Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4
Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4
Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8
Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Software Design Considerations for Multiple Processors . . .. . . . . 1–9
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13
Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15
Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15
Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16
Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17
Getting Started with the multiprocessor_tutorial_start Design Example 1–17
Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19
Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22
Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27
Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
標(biāo)簽：
Nios
處理器
多處理器
上傳時(shí)間：
2013-11-21
上傳用戶：lo25643
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使用Nios II緊耦合存儲(chǔ)器教程
Chapter 1. Using Tightly Coupled Memory with the Nios II Processor
Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1
Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2
Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3
Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3
Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5
Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
標(biāo)簽：
Nios
耦合
存儲(chǔ)器
教程
上傳時(shí)間：
2013-10-13
上傳用戶：黃婷婷思密達(dá)
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This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, Memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽：
Spartan
XAPP
FPGA
098
上傳時(shí)間：
2013-11-01
上傳用戶：wojiaohs
