This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) Memory feedback clock. In this system, theDDR Memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM Memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the Memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct Memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM Memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
微電腦型RS-485顯示電表（24*48mm/48*96mm） 特點： 5位數RS-485顯示電表 顯示范圍-19999-99999位數 通訊協議Modbus RTU模式 寬范圍交直流兩用電源設計 尺寸小,穩定性高 主要規格： 顯示范圍:-19999~99999 digit RS-485傳輸速度: 19200/9600/4800/2400 selective RS-485通訊位址: "01"-"FF" RS-485通訊協議: Modbus RTU mode 顯示幕: Red high efficiency LEDs high 10.16 mm (0.4") (MMX-RS-11X) Red high efficiency LEDs high 20.32 mm (0.8") (MMX-RS-12X) Red high efficiency LEDs high 10.16 mm (0.4")x2 (MMX-RS-22X) 參數設定方式: Touch switches 記憶方式: Non-volatile E²PROM Memory 絕緣耐壓能力: 2KVac/1 min. (input/power) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available Memory tostore the data.
Semiconductor Memory, card readers, microprocessors,disc drives, piezoelectric devices and digitally based systemsfurnish transient loads that a voltage regulator mustservice. Ideally, regulator output is invariant during a loadtransient. In practice, some variation is encountered andbecomes problematic if allowable operating voltage tolerancesare exceeded. This mandates testing the regulatorand its associated support components to verify desiredperformance under transient loading conditions. Variousmethods are employable to generate transient loads, allowingobservation of regulator response
