This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
標(biāo)簽： Virtex TEMAC XAPP 1023
上傳時(shí)間： 2013-11-11
上傳用戶：saharawalker
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data rateMode or a high-speed data download Mode for assembly line andservice data transfer operations. The high-speed Mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep Mode current.
上傳時(shí)間： 2013-10-24
上傳用戶：s藍(lán)莓汁
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽： lpc datasheet 2292 2294
上傳時(shí)間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: This application note describes system-level characterization and Modeling techniques for radio frequency (RF) and microwavesubsystem components. It illustrates their use in a mixed-signal, mixed-Mode system-level simulation. The simulation uses an RF transmitterwith digital predistortion (DPD) as an example system. Details of this complex system and performance data are presented.
標(biāo)簽： 射頻 仿真 微波系統(tǒng) 建模
上傳時(shí)間： 2013-12-18
上傳用戶：onewq
為滿足無線網(wǎng)絡(luò)技術(shù)具有低功耗、節(jié)點(diǎn)體積小、網(wǎng)絡(luò)容量大、網(wǎng)絡(luò)傳輸可靠等技術(shù)要求，設(shè)計(jì)了一種以MSP430單片機(jī)和CC2420射頻收發(fā)器組成的無線傳感節(jié)點(diǎn)。通過分析其節(jié)點(diǎn)組成，提出了ZigBee技術(shù)中的幾種網(wǎng)絡(luò)拓?fù)湫问?，并研究了ZigBee路由算法。針對(duì)不同的傳輸要求形式選用不同的網(wǎng)絡(luò)拓?fù)湫问娇梢员M大可能地減少系統(tǒng)成本。同時(shí)針對(duì)不同網(wǎng)絡(luò)選用正確的ZigBee路由算法有效地減少了網(wǎng)絡(luò)能量消耗，提高了系統(tǒng)的可靠性。應(yīng)用試驗(yàn)表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統(tǒng)的有線通信方式相比可以節(jié)約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission Mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee Mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications Mode.
標(biāo)簽： ZigBee 無線傳感網(wǎng)絡(luò) 協(xié)議研究 路由
上傳時(shí)間： 2013-10-09
上傳用戶：robter
Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element Models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed Models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-Mode S-parameters,” addresses differential and common-Mode operation, as well as the conversion betweenthe two Modes of operation.This application note will explain the use of single-ended and mixed-Mode S-parameters, and the basicconcepts of microwave measurement calibration.
上傳時(shí)間： 2014-03-25
上傳用戶：yyyyyyyyyy
The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) Mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby Mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上傳時(shí)間： 2014-01-04
上傳用戶：LANCE
基本的編輯工具(GENERAL EDITING FACILITIES) 對(duì)象放置(Object Placement) ISIS支持多種類型的對(duì)象，每一類型對(duì)象的具體作用和功能將在下一章給出。雖然類型不同，但放置對(duì)象的基本步驟都是一樣的。 放置對(duì)象的步驟如下(To place an object:) 1.根據(jù)對(duì)象的類別在工具箱選擇相應(yīng)模式的圖標(biāo)(Mode icon)。 2. Select the sub-Mode icon for the specific type of object. 2、根據(jù)對(duì)象的具體類型選擇子模式圖標(biāo)(sub-Mode icon)。 3、如果對(duì)象類型是元件、端點(diǎn)、管腳、圖形、符號(hào)或標(biāo)記，從選擇器里(selector)選擇你想要的對(duì)象的名字。對(duì)于元件、端點(diǎn)、管腳和符號(hào)，可能首先需要從庫中調(diào)出。 4、如果對(duì)象是有方向的，將會(huì)在預(yù)覽窗口顯示出來，你可以通過點(diǎn)擊旋轉(zhuǎn)和鏡象圖標(biāo)來調(diào)整對(duì)象的朝向。 5、最后，指向編輯窗口并點(diǎn)擊鼠標(biāo)左鍵放置對(duì)象。對(duì)于不同的對(duì)象，確切的步驟可能略有不同，但你會(huì)發(fā)現(xiàn)和其它的圖形編輯軟件是類似的，而且很直觀。 選中對(duì)象(Tagging an Object) 用鼠標(biāo)指向?qū)ο蟛Ⅻc(diǎn)擊右鍵可以選中該對(duì)象。該操作選中對(duì)象并使其高亮顯示，然后可以進(jìn)行編輯。
上傳時(shí)間： 2013-10-29
上傳用戶：avensy
3 FPGA設(shè)計(jì)流程 完整的FPGA 設(shè)計(jì)流程包括邏輯電路設(shè)計(jì)輸入、功能仿真、綜合及時(shí)序分析、實(shí)現(xiàn)、加載配置、調(diào)試。FPGA 配置就是將特定的應(yīng)用程序設(shè)計(jì)按FPGA設(shè)計(jì)流程轉(zhuǎn)化為數(shù)據(jù)位流加載到FPGA 的內(nèi)部存儲(chǔ)器中，實(shí)現(xiàn)特定邏輯功能的過程。由于FPGA 電路的內(nèi)部存儲(chǔ)器都是基于RAM 工藝的，所以當(dāng)FPGA電路電源掉電后，內(nèi)部存儲(chǔ)器中已加載的位流數(shù)據(jù)將隨之丟失。所以，通常將設(shè)計(jì)完成的FPGA 位流數(shù)據(jù)存于外部存儲(chǔ)器中，每次上電自動(dòng)進(jìn)行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，F(xiàn)PGA的配置模式有四種方案可選擇：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復(fù)用引腳信號(hào)完成的，主要配置功能信號(hào)如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時(shí)鐘信號(hào); (3)DONE：顯示配置狀態(tài)、控制器件啟動(dòng);
標(biāo)簽： Xilinx FPGA 集成電路 動(dòng)態(tài)老化
上傳時(shí)間： 2013-11-18
上傳用戶：oojj
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express Mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標(biāo)簽： Spartan-XL Express XAPP FPGA
上傳時(shí)間： 2015-01-02
上傳用戶：nanxia
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