the vhdl model of usb. it is very helpful.
標(biāo)簽： helpful model vhdl very
上傳時(shí)間： 2014-01-21
上傳用戶：zhyiroy
人工智能中模糊邏輯算法 FuzzyLib 2.0 is a comprehensive C++ Fuzzy Logic library for constructing fuzzy logic systems with multi-controller support. It supports all commonly used shape functions and hedges, with full support for the various types of Aggregation, Correlation, Alphacut, Composition, Defuzzification methods. The latest version of the C++ Fuzzy Logic Class Library contains all the C++ source code and comes complete with a usage example for building a multi-controllers fuzzy logic model.
標(biāo)簽： comprehensive constructing FuzzyLib library
上傳時(shí)間： 2013-12-17
上傳用戶：dbs012280
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Space, I/O Index/Data, Super I/O, Clock Generator, DIMM SPD, SMBus Device, CPU MSR Registers, ATA/ATAPI Identify Data, ACPI Tables Dump (include AML decode), Embedded Controller, USB Information and LPT Remote Access. And also an Command Window is provided to access hardware manually. Website1: http://rw.net-forces.com/ Website2: http://home.kimo.com.tw/ckimchan.tw/ Website3: http://jacky5488.myweb.hinet.net/ For best view, please change the screen resolution to 1024 x 768 (or above) pixels.
標(biāo)簽： engineers developers firmware hardware
上傳時(shí)間： 2013-12-22
上傳用戶：王楚楚
Capability Maturity Model Integration, Version 1.1 CMMI for Systems Engineering and Software Engineering
標(biāo)簽： Integration Engineering Capability Maturity
上傳時(shí)間： 2015-07-11
上傳用戶：hphh
ucos-view 找了很久，只有1.10的，大家參考一下吧
標(biāo)簽： ucos-view
上傳時(shí)間： 2014-08-10
上傳用戶：lz4v4
inside the c++ object model.深入c++對象模型。鼎鼎大名的Stanley B. Lippman 寫的。搞c++編程的能不看嗎？
標(biāo)簽： B. Stanley Lippman inside
上傳時(shí)間： 2013-12-22
上傳用戶：佳期如夢
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)
標(biāo)簽： microcontroller Synthesizable ATmega Atmel
上傳時(shí)間： 2013-11-30
上傳用戶：z754970244
Example of a digital data transmission implementing GMSK modulation This Simulink model simulates as an example the transmission and reception of random digital data modulated with GMSK. The purpose of this model is to illustrate how part of the GSM transmission and reception works. It also measures the BER, affected by an AWGN channel
標(biāo)簽： implementing transmission modulation simulates
上傳時(shí)間： 2015-07-12
上傳用戶：jiahao131
Simulator for a GSM traffic channel transmission and reception This Simulink model simulates the entire transmission and reception of voice data of a traffic channel for GSM (TCH/FS)over a multipath fading channel, and it calculates the BER of the received signal
標(biāo)簽： transmission Simulator reception simulates
上傳時(shí)間： 2015-07-12
上傳用戶：BIBI
RAKE receiver for direct-sequence spread spectrum systems Simulink model of a simple direct-sequence spread spectrum system with RAKE reception
標(biāo)簽： direct-sequence direct-sequenc receiver Simulink
上傳時(shí)間： 2014-01-05
上傳用戶：lunshaomo
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