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<li id="c4448"></li> 對(duì)講機(jī)常用術(shù)語 對(duì)講機(jī), 術(shù)語 [watermark] 監(jiān)聽（Monitor） 為接受弱小信號(hào)而采用的一種收聽方式。
標(biāo)簽： 對(duì)講機(jī) 術(shù)語
上傳時(shí)間： 2013-11-21
上傳用戶：
嵌入式系統(tǒng)是一種應(yīng)用范圍非常廣泛的系統(tǒng)。可以說除了桌面計(jì)算機(jī)和服務(wù)器外所有計(jì)算設(shè)備都屬于嵌入式系統(tǒng)，例如從便攜式音樂播放器到航天飛機(jī)上的實(shí)時(shí)系統(tǒng)控制都屬于嵌入式系統(tǒng)。 大多數(shù)商用的嵌入式系統(tǒng)都設(shè)計(jì)成專用任務(wù)的低成本的產(chǎn)品。大多數(shù)的嵌入式系統(tǒng)都具有實(shí)時(shí)性的要求。有些功能需要非常快的主頻，但其他大多數(shù)功能并不需要高速的處理能力。這些系統(tǒng)通過特定的器件和軟件來滿足實(shí)時(shí)性的要求。 簡單地通過速度和成本來定義嵌入式系統(tǒng)是困難的，但對(duì)于大批量的產(chǎn)品而言，成本常常對(duì)系統(tǒng)設(shè)計(jì)起決定作用。通常，一個(gè)嵌入式系統(tǒng)的很多部分相對(duì)系統(tǒng)主要功能來說需要較低的性能，因此嵌入式系統(tǒng)和通用PC相比，能夠使用一個(gè)滿足輔助功能的合適的CPU，從而簡化了系統(tǒng)設(shè)計(jì)，降低了成本。例如，數(shù)字電視的機(jī)頂盒需要處理每秒以百萬兆位計(jì)的連續(xù)數(shù)據(jù)，但這些數(shù)據(jù)處理大部分是由定制的硬件來實(shí)現(xiàn)的，如解析、管理和編解碼多個(gè)頻道的數(shù)字影像。 對(duì)于大批量生產(chǎn)的嵌入式系統(tǒng)，如便攜式音樂播放器或手機(jī)等，降低成本就成為最主要的問題。這些系統(tǒng)通常只具有幾個(gè)芯片：一個(gè)高度集成的CPU，一個(gè)定制的芯片用于控制其他所有的功能，還有一個(gè)存儲(chǔ)芯片。在這種設(shè)計(jì)中，每部分都設(shè)計(jì)成使用最小的系統(tǒng)功耗。 對(duì)于小批量的嵌入式應(yīng)用，為了降低開發(fā)成本，常常使用PC體系結(jié)構(gòu)，通過限制程序的執(zhí)行時(shí)間或用一個(gè)實(shí)時(shí)操作系統(tǒng)來替換原先的操作系統(tǒng)。在這種情況下，可以使用一個(gè)或多個(gè)高性能的CPU來替換特殊用途的硬件。 嵌入式系統(tǒng)的軟件通常運(yùn)行在有限的硬件資源上：沒有硬盤、操作系統(tǒng)、鍵盤或屏幕。軟件一般都沒有文件系統(tǒng)，如果有的話，也會(huì)采用Flash驅(qū)動(dòng)器。如果有人機(jī)交互接口的話，也是一個(gè)小鍵盤或液晶顯示器。硬件是計(jì)算機(jī)的物理部分，和存儲(chǔ)在硬件中的計(jì)算機(jī)軟件程序和數(shù)據(jù)區(qū)分開來。 嵌入到機(jī)械中的嵌入式系統(tǒng)需要長期無故障連續(xù)運(yùn)行，因此它的軟件需要比PC中的軟件更加仔細(xì)地開發(fā)和更加嚴(yán)格地測試。 那么，到底什么是嵌入式系統(tǒng)呢？ 根據(jù)IEEE（國際電氣和電子工程師協(xié)會(huì)）的定義，嵌入式系統(tǒng)是“控制、監(jiān)視或者輔助設(shè)備、機(jī)器和車間運(yùn)行的裝置”（原文為devices used to control，Monitor，or assist the operation of equipment，machinery or plants）。這主要是從應(yīng)用上加以定義的，從中可以看出嵌入式系統(tǒng)是軟件和硬件的綜合體，還可以涵蓋機(jī)械等附屬裝置。 目前國內(nèi)一個(gè)普遍被認(rèn)同的定義是：以應(yīng)用為中心、以計(jì)算機(jī)技術(shù)為基礎(chǔ)，軟件 硬件可裁剪，適應(yīng)應(yīng)用系統(tǒng)對(duì)功能、可靠性、成本、體積、功耗嚴(yán)格要求的專用計(jì)算機(jī)系統(tǒng)。 可以這樣認(rèn)為，嵌入式系統(tǒng)是一種專用的計(jì)算機(jī)系統(tǒng)，作為裝置或設(shè)備的一部分。通常，嵌入式系統(tǒng)是一個(gè)控制程序存儲(chǔ)在ROM中的嵌入式處理器控制板。事實(shí)上，所有帶有數(shù)字接口的設(shè)備，如手表、微波爐、錄像機(jī)、汽車等，都使用嵌入式系統(tǒng)，有些嵌入式系統(tǒng)還包含操作系統(tǒng)，但大多數(shù)嵌入式系統(tǒng)都是由單個(gè)程序?qū)崿F(xiàn)整個(gè)控制邏輯。 本書是按照人事部、信息產(chǎn)業(yè)部全國計(jì)算機(jī)技術(shù)與軟件專業(yè)技術(shù)資格（水平）考試要求編寫，內(nèi)容緊扣《嵌入式系統(tǒng)設(shè)計(jì)考試大鋼》。全書共六章，分別對(duì)嵌入式系統(tǒng)基礎(chǔ)知識(shí)、嵌入式微處理器與接口設(shè)計(jì)、嵌入式軟件與操作系統(tǒng)、嵌入式軟件程序設(shè)計(jì)、嵌入式系統(tǒng)設(shè)計(jì)與維護(hù)等知識(shí)進(jìn)行了詳細(xì)的講解。最后介紹了一個(gè)典型的嵌入式系統(tǒng)設(shè)計(jì)案例。 本書內(nèi)容豐富，結(jié)構(gòu)合理，概念清晰。既可作為全國計(jì)算機(jī)技術(shù)與軟件專業(yè)技術(shù)資格（水平）考試中嵌入式系統(tǒng)設(shè)計(jì)師級(jí)別的考試用書，供有關(guān)考生學(xué)習(xí)使用，也可作為本科生嵌入式系統(tǒng)相關(guān)課程教材或培訓(xùn)書使用。
標(biāo)簽： 嵌入式 系統(tǒng)設(shè)計(jì)師 教程
上傳時(shí)間： 2013-10-29
上傳用戶：dongqiangqiang
6小時(shí)學(xué)會(huì)labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽： labview
上傳時(shí)間： 2013-10-13
上傳用戶：zjwangyichao
Abstract: Most hand-held products lack accurate battery-charge Monitors ("fuel gauges") because of the misconception that an accurate fuel gauge is difficult to achieve. This article debunks the myths and discusses how to accurately Monitor charge at all temperatures, charge and discharge rates, and aging conditions. 無線通信和數(shù)據(jù)在新一代手機(jī)和PDA中的融合為再一次的生產(chǎn)力飛躍創(chuàng)造了條件。。隨之而來的將是經(jīng)濟(jì)的增長和全新的工作方式，在便攜式計(jì)算機(jī)領(lǐng)域，PC筆記本曾經(jīng)扮演了類似的開拓者角角。
標(biāo)簽： 錯(cuò)誤 電量計(jì) 無線 手機(jī)
上傳時(shí)間： 2013-10-17
上傳用戶：erkuizhang
Abstract: Most hand-held products lack accurate battery-charge Monitors ("fuel gauges") because of the misconception that an accurate fuel gauge is difficult to achieve. This article debunks the myths and discusses how to accurately Monitor charge at all temperatures, charge and discharge rates, and aging conditions.
標(biāo)簽： 錯(cuò)誤 電量計(jì) 無線 手機(jī)
上傳時(shí)間： 2014-03-18
上傳用戶：wenwiang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance Monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily Monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標(biāo)簽： FPGA PLD 數(shù)據(jù)加密
上傳時(shí)間： 2013-10-20
上傳用戶：磊子226
Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA Monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB開發(fā)
標(biāo)簽： system configuration recommends following
上傳時(shí)間： 2015-03-27
上傳用戶：13188549192
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to Monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標(biāo)簽： the Analyzer Compiler project
上傳時(shí)間： 2013-12-19
上傳用戶：Yukiseop
Displays CPU time usage, the list of processes (can be terminated) and the task which are running (can be close or switch to). Plus a little net traffic Monitor and a disk status report.
標(biāo)簽： terminated the processes Displays
上傳時(shí)間： 2013-12-25
上傳用戶：zgu489
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