FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上傳時間： 2013-10-13
上傳用戶：13162218709
The PAM2862 is a continuous mode inductivestep-down converter, designed for driving singleor multiple series connected LEDs efficientlyfrom a voltage source higher than the LEDvoltage. The device operates from an inputupply between 6V and 30V and provides anexternally adjustable output current of up to 1A.Depending upon supply voltage and externalcomponents, this can provide up to 24 watts ofoutput power.
上傳時間： 2013-11-16
上傳用戶：司令部正軍級
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標簽： 4channel multiple 9544A 9544
上傳時間： 2014-12-28
上傳用戶：潛水的三貢
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
為了擴大監(jiān)控范圍，提高資源利用率，降低系統(tǒng)成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據(jù)行場信號由DSP和FPGA產(chǎn)生控制信號，控制多路視頻通道之間的切換，從而實現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實驗結果表明，該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實現(xiàn)視頻通道的切換。 Abstract: To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus， it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
上傳時間： 2013-11-09
上傳用戶：不懂夜的黑
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
很多不同的廠家生產(chǎn)各種型號的計算機，它們運行完全不同的操作系統(tǒng)，但TCP.IP協(xié)議族允許它們互相進行通信。這一點很讓人感到吃驚，因為它的作用已遠遠超出了起初的設想。T C P / I P起源于6 0年代末美國政府資助的一個分組交換網(wǎng)絡研究項目，到9 0年代已發(fā)展成為計算機之間最常應用的組網(wǎng)形式。它是一個真正的開放系統(tǒng)，因為協(xié)議族的定義及其多種實現(xiàn)可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯(lián)網(wǎng)”或“因特網(wǎng)(Internet)”的基礎，該廣域網(wǎng)（WA N）已包含超過1 0 0萬臺遍布世界各地的計算機。本章主要對T C P / I P協(xié)議族進行概述，其目的是為本書其余章節(jié)提供充分的背景知識。 TCP.IP協(xié)議 縮略語 ACK (ACKnowledgment) TCP首部中的確認標志 API (Application Programming Interface) 應用編程接口 ARP (Address Resolution Protocol) 地址解析協(xié)議 ARPANET(Defense Advanced Research Project Agency NETwork) (美國)國防部遠景研究規(guī)劃局 AS (Autonomous System) 自治系統(tǒng) ASCII (American Standard Code for Information Interchange) 美國信息交換標準碼 ASN.1 (Abstract Syntax Notation One) 抽象語法記法1 BER (Basic Encoding Rule) 基本編碼規(guī)則 BGP (Border Gateway Protocol) 邊界網(wǎng)關協(xié)議 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引導程序協(xié)議 BPF (BSD Packet Filter) BSD 分組過濾器 CIDR (Classless InterDomain Routing) 無類型域間選路 CIX (Commercial Internet Exchange) 商業(yè)互聯(lián)網(wǎng)交換 CLNP (ConnectionLess Network Protocol) 無連接網(wǎng)絡協(xié)議 CRC (Cyclic Redundancy Check) 循環(huán)冗余檢驗 CSLIP (Compressed SLIP) 壓縮的S L I P CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取 DCE (Data Circuit-terminating Equipment) 數(shù)據(jù)電路端接設備 DDN (Defense Data Network) 國防數(shù)據(jù)網(wǎng) DF (Don’t Fragment) IP首部中的不分片標志 DHCP (Dynamic Host Configuration Protocol) 動態(tài)主機配置協(xié)議 DLPI (Data Link Provider Interface) 數(shù)據(jù)鏈路提供者接口 DNS (Domain Name System) 域名系統(tǒng) DSAP (Destination Service Access Point) 目的服務訪問點 DSLAM (DSL Access Multiplexer) 數(shù)字用戶線接入復用器 DSSS (Direct Sequence Spread Spectrum) 直接序列擴頻 DTS (Distributed Time Service) 分布式時間服務 DVMRP (Distance Vector Multicast Routing Protocol) 距離向量多播選路協(xié)議 EBONE (European IP BackbONE) 歐洲I P主干網(wǎng) EOL (End of Option List) 選項清單結束 EGP (External Gateway Protocol) 外部網(wǎng)關協(xié)議 EIA (Electronic Industries Association) 美國電子工業(yè)協(xié)會 FCS (Frame Check Sequence) 幀檢驗序列 FDDI (Fiber Distributed Data Interface) 光纖分布式數(shù)據(jù)接口 FIFO (First In, First Out) 先進先出 FIN (FINish) TCP首部中的結束標志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件傳送協(xié)議 HDLC (High-level Data Link Control) 高級數(shù)據(jù)鏈路控制 HELLO 選路協(xié)議 IAB (Internet Architecture Board) Internet體系結構委員會 IANA (Internet Assigned Numbers Authority) Internet號分配機構 ICMP (Internet Control Message Protocol) Internet控制報文協(xié)議 IDRP (InterDomain Routing Protocol) 域間選路協(xié)議 IEEE (Institute of Electrical and Electronics Engineering) （美國）電氣與電子工程師協(xié)會 IEN (Internet Experiment Notes) 互聯(lián)網(wǎng)試驗注釋 IESG (Internet Engineering Steering Group) Internet工程指導小組 IETF (Internet Engineering Task Force) Internet工程專門小組 IGMP (Internet Group Management Protocol) Internet組管理協(xié)議 IGP (Interior Gateway Protocol) 內(nèi)部網(wǎng)關協(xié)議 IMAP (Internet Message Access Protocol) Internet報文存取協(xié)議 IP (Internet Protocol) 網(wǎng)際協(xié)議 I RTF (Internet Research Task Force) Internet研究專門小組 IS-IS (Intermediate System to Intermediate System Protocol) 中間系統(tǒng)到中間系統(tǒng)協(xié)議 ISN (Initial Sequence Number) 初始序號 ISO (International Organization for Standardization) 國際標準化組織 ISOC (Internet SOCiety) Internet協(xié)會 LAN (Local Area Network) 局域網(wǎng) LBX (Low Bandwidth X) 低帶寬X LCP (Link Control Protocol) 鏈路控制協(xié)議 LFN (Long Fat Net) 長肥網(wǎng)絡 LIFO (Last In, First Out) 后進先出 LLC (Logical Link Control) 邏輯鏈路控制 LSRR (Loose Source and Record Route) 寬松的源站及記錄路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網(wǎng) MIB (Management Information Base) 管理信息庫 MILNET (MILitary NETwork) 軍用網(wǎng) MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴充 MSL (Maximum Segment Lifetime) 報文段最大生存時間 MSS (Maximum Segment Size) 最大報文段長度 M TA (Message Transfer Agent) 報文傳送代理 MTU (Maximum Transmission Unit) 最大傳輸單元 NCP (Network Control Protocol) 網(wǎng)絡控制協(xié)議 NFS (Network File System) 網(wǎng)絡文件系統(tǒng) NIC (Network Information Center) 網(wǎng)絡信息中心 NIT (Network Interface Tap) 網(wǎng)絡接口栓（S u n公司的一個程序） NNTP (Network News Transfer Protocol) 網(wǎng)絡新聞傳送協(xié)議 NOAO (National Optical Astronomy Observatories) 國家光學天文臺 NOP (No Operation) 無操作 NSFNET (National Science Foundation NETwork) 國家科學基金網(wǎng)絡 NSI (NASA Science Internet) （美國）國家宇航局I n t e r n e t NTP (Network Time Protocol) 網(wǎng)絡時間協(xié)議 NVT (Network Virtual Terminal) 網(wǎng)絡虛擬終端 OSF (Open Software Foudation) 開放軟件基金 OSI (Open Systems Interconnection) 開放系統(tǒng)互連 OSPF (Open Shortest Path First) 開放最短通路優(yōu)先 PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號 PDU (Protocol Data Unit) 協(xié)議數(shù)據(jù)單元 POSIX (Portable Operating System Interface) 可移植操作系統(tǒng)接口 PPP (Point-to-Point Protocol) 點對點協(xié)議 PSH (PuSH) TCP首部中的急迫標志 RARP (Reverse Address Resolution Protocol) 逆地址解析協(xié)議 RFC (Request For Comments) Internet的文檔，其中的少部分成為標準文檔 RIP (Routing Information Protocol) 路由信息協(xié)議 RPC (Remote Procedure Call) 遠程過程調用 RR (Resource Record) 資源記錄 RST (ReSeT) TCP首部中的復位標志 RTO (Retransmission Time Out) 重傳超時 RTT (Round-Trip Time) 往返時間 SACK (Selective ACKnowledgment) 有選擇的確認 SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協(xié)議 SMI (Structure of Management Information) 管理信息結構 SMTP (Simple Mail Transfer Protocol) 簡單郵件傳送協(xié)議 SNMP (Simple Network Management Protocol) 簡單網(wǎng)絡管理協(xié)議 SSAP (Source Service Access Point) 源服務訪問點 SSRR (Strict Source and Record Route) 嚴格的源站及記錄路由 SWS (Silly Window Syndrome) 糊涂窗口綜合癥 SYN (SYNchronous) TCP首部中的同步序號標志 TCP (Transmission Control Protocol) 傳輸控制協(xié)議 TFTP (Trivial File Transfer Protocol) 簡單文件傳送協(xié)議 TLI (Transport Layer Interface) 運輸層接口 TTL (Ti m e - To-Live) 生存時間或壽命 TUBA (TCP and UDP with Bigger Addresses) 具有更長地址的T C P和U D P Telnet 遠程終端協(xié)議 UA (User Agent) 用戶代理 UDP (User Datagram Protocol) 用戶數(shù)據(jù)報協(xié)議 URG (URGent) TCP首部中的緊急指針標志 UTC (Coordinated Universal Time) 協(xié)調的統(tǒng)一時間 UUCP (Unix-to-Unix CoPy) Unix到U n i x的復制 WAN (Wide Area Network) 廣域網(wǎng) WWW (World Wide Web) 萬維網(wǎng) XDR (eXternal Data Representation) 外部數(shù)據(jù)表示 XID (transaction ID) 事務標識符 XTI (X/Open Transport Layer Interface) X/ O p e n運輸層接口
上傳時間： 2013-11-13
上傳用戶：tdyoung
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上傳時間： 2013-10-26
上傳用戶：agent
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
