In the last three articles, I’ve been walking you through the creation of an end-to-end BlackBerry application that will serve as a mobile front-end to my Knowledge Base sample web application.
標簽： BlackBerry end-to-end the articles
上傳時間： 2014-01-25
上傳用戶：kristycreasy
What I am trying to introduce here is a full fledged Java Instant messenger, which has all the features supplied by commercial messengers like Yahoo or MSN. Although it cannot compared to be in par with those messengers, it is an attempt by me to learn Advanced Java and JNI concepts. The challenges I faced here were often overcome by referring to numerous sites, which nearly zeroes in or completely solved the issues I faced at that point of time. It improved my learning curve and also believe would do the same to you too. Ofcourse, there are some bugs and glitches, which I hope you would excuse. Thanks to anyone who takes the pain to report them or even suggest better way of doing things to me.
標簽： introduce messenger Instant fledged
上傳時間： 2014-12-05
上傳用戶：電子世界
一個簡單而精彩的java聊天室小程序，用my eclipse5.0寫的,有客戶端和服務端.
上傳時間： 2014-01-06
上傳用戶：a673761058
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
標簽： synthesize simulator modelsim interin
上傳時間： 2017-03-22
上傳用戶：洛木卓
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
標簽： synthesize simulator modelsim digital
上傳時間： 2014-01-10
上傳用戶：kernaling
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
標簽： synthesize simulator modelsim verilog
上傳時間： 2014-06-26
上傳用戶：zhuyibin
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
標簽： controller synthesize verilog traffic
上傳時間： 2017-03-22
上傳用戶：xymbian
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
標簽： synthesize verilog machine written
上傳時間： 2013-12-11
上傳用戶：yepeng139
本源碼是jsp編寫的圖書管理系統，采用的數據庫是my sql，內有使用說明和系統模塊介紹
上傳時間： 2017-03-30
上傳用戶：liuchee
TMS6713b receiving by McBSP & EDMA(with reconfiguration of the port depending on taken given) excuse me for my english
標簽： reconfiguration receiving depending excuse
上傳時間： 2017-04-12
上傳用戶：sammi
