The CAT9534 is an 8-bit parallel input/OUTPUT portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anOUTPUT port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
上傳時(shí)間： 2013-11-09
上傳用戶：liulinshan2010
基于PIC單片機(jī)的脈沖電源:設(shè)計(jì)了一種金屬凝固過程用脈沖電源。該電源采用PIC16F877作為主控芯片，實(shí)現(xiàn)對(duì)窄脈沖電流幅值的檢測(cè)，以及時(shí)電流脈沖幅值根據(jù)模糊PID算法進(jìn)行閑環(huán)控制。使用結(jié)果表明：該電源的輸出脈沖波形良好，電流幅值穩(wěn)定，滿足合金材料凝固過程的工藝要求且運(yùn)行穩(wěn)定可靠。關(guān)鍵詞：脈沖電源；PIC16F877單片機(jī)；模糊PID；閑環(huán)控制 Abstract：A kind of pulse power supply was designed which uses in the metal solidification process ．．I11is power supply used PIC16F877 to take the master control chip reali on to the narrow pulse electric current peak-to-peak value examination，carried on the closed-loop control to the electric current pulse peak-to-peak value basis fuzzy PID algorithm．The use result indicated ，this power supply OUTPUT se profile is good，and the electric current peak-to-p~k value is stable，It satisfies the alloy material solidification process the technological requirement and movement stable reliable，Key words：p se po wer supply；PIC16F877single-chip microcontroller；f r PID；closed-loop control
上傳時(shí)間： 2013-10-27
上傳用戶：xcy122677
有兩種方式可以讓設(shè)備和應(yīng)用程序之間聯(lián)系：1. 通過為設(shè)備創(chuàng)建的一個(gè)符號(hào)鏈；2. 通過輸出到一個(gè)接口WDM驅(qū)動(dòng)程序建議使用輸出到一個(gè)接口而不推薦使用創(chuàng)建符號(hào)鏈的方法。這個(gè)接口保證PDO的安全，也保證安全地創(chuàng)建一個(gè)惟一的、獨(dú)立于語(yǔ)言的訪問設(shè)備的方法。一個(gè)應(yīng)用程序使用Win32APIs來調(diào)用設(shè)備。在某個(gè)Win32 APIs和設(shè)備對(duì)象的分發(fā)函數(shù)之間存在一個(gè)映射關(guān)系。獲得對(duì)設(shè)備對(duì)象訪問的第一步就是打開一個(gè)設(shè)備對(duì)象的句柄。 用符號(hào)鏈打開一個(gè)設(shè)備的句柄為了打開一個(gè)設(shè)備，應(yīng)用程序需要使用CreateFile。如果該設(shè)備有一個(gè)符號(hào)鏈出口，應(yīng)用程序可以用下面這個(gè)例子的形式打開句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路徑名的前綴“\\.\”告訴系統(tǒng)本調(diào)用希望打開一個(gè)設(shè)備。這個(gè)設(shè)備必須有一個(gè)符號(hào)鏈，以便應(yīng)用程序能夠打開它。有關(guān)細(xì)節(jié)查看有關(guān)Kdevice和CreateLink的內(nèi)容。在上述調(diào)用中第一個(gè)參數(shù)中前綴后的部分就是這個(gè)符號(hào)鏈的名字。注意：CreatFile中的第一個(gè)參數(shù)不是Windows 98/2000中驅(qū)動(dòng)程序(.sys文件)的路徑。是到設(shè)備對(duì)象的符號(hào)鏈。如果使用DriverWizard產(chǎn)生驅(qū)動(dòng)程序，它通常使用類KunitizedName來構(gòu)成設(shè)備的符號(hào)鏈。這意味著符號(hào)鏈名有一個(gè)附加的數(shù)字，通常是0。例如：如果鏈接名稱的主干是L“TestDevice”那么在CreateFile中的串就該是“\\\\.\\TestDevice0”。如果應(yīng)用程序需要被覆蓋的I/O，第六個(gè)參數(shù)(Flags)必須或上FILE_FLAG_OVERLAPPED。 使用一個(gè)輸出接口打開句柄用這種方式打開一個(gè)句柄會(huì)稍微麻煩一些。DriverWorks庫(kù)提供兩個(gè)助手類來使獲得對(duì)該接口的訪問容易一些，這兩個(gè)類是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass類封裝了一個(gè)設(shè)備信息集，該信息集包含了特殊類中的所有設(shè)備接口信息。應(yīng)用程序能有用CdeviceInterfaceClass類的一個(gè)實(shí)例來獲得一個(gè)或更多的CdeviceInterface類的實(shí)例。CdeviceInterface類是一個(gè)單一設(shè)備接口的抽象。它的成員函數(shù)DevicePath()返回一個(gè)路徑名的指針，該指針可以在CreateFile中使用來打開設(shè)備。下面用一個(gè)小例子來顯示這些類最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在設(shè)備中執(zhí)行I/O操作一旦應(yīng)用程序獲得一個(gè)有效的設(shè)備句柄，它就能使用Win32 APIs來產(chǎn)生到設(shè)備對(duì)象的IRPs。下面的表顯示了這種對(duì)應(yīng)關(guān)系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解釋一下設(shè)備類成員的Close和CleanUp：CreateFile使內(nèi)核為設(shè)備創(chuàng)建一個(gè)新的文件對(duì)象。這使得多個(gè)句柄可以映射同一個(gè)文件對(duì)象。當(dāng)這個(gè)文件對(duì)象的最后一個(gè)用戶級(jí)句柄被撤銷后，I/O管理器調(diào)用CleanUp。當(dāng)沒有任何用戶級(jí)和核心級(jí)的對(duì)文件對(duì)象的訪問的時(shí)候，I/O管理器調(diào)用Close。如果被打開的設(shè)備不支持指定的功能，則調(diào)用相應(yīng)的Win32將引起錯(cuò)誤（無(wú)效功能）。以前為Windows95編寫的VxD的應(yīng)用程序代碼中可能會(huì)在打開設(shè)備的時(shí)候使用FILE_FLAG_DELETE_ON_CLOSE屬性。在Windows NT/2000中，建議不要使用這個(gè)屬性，因?yàn)樗鼘?dǎo)致沒有特權(quán)的用戶企圖打開這個(gè)設(shè)備，這是不可能成功的。I/O管理器將ReadFile和WriteFile的buff參數(shù)轉(zhuǎn)換成IRP域的方法依賴于設(shè)備對(duì)象的屬性。當(dāng)設(shè)備設(shè)置DO_DIRECT_IO標(biāo)志，I/O管理器將buff鎖住在存儲(chǔ)器中，并且創(chuàng)建了一個(gè)存儲(chǔ)在IRP中的MDL域。一個(gè)設(shè)備可以通過調(diào)用Kirp::Mdl來存取MDL。當(dāng)設(shè)備設(shè)置DO_BUFFERED_IO標(biāo)志，設(shè)備對(duì)象分別通過KIrp::BufferedReadDest或 KIrp::BufferedWriteSource為讀或?qū)懖僮鳙@得buff地址。當(dāng)設(shè)備不設(shè)置DO_BUFFERED_IO標(biāo)志也不設(shè)置DO_DIRECT_IO，內(nèi)核設(shè)置IRP 的UserBuffer域來對(duì)應(yīng)ReadFile或WriteFile中的buff參數(shù)。然而，存儲(chǔ)區(qū)并沒有被鎖住而且地址只對(duì)調(diào)用進(jìn)程有效。驅(qū)動(dòng)程序可以使用KIrp::UserBuffer來存取IRP域。對(duì)于DeviceIoControl調(diào)用，buffer參數(shù)的轉(zhuǎn)換依賴于特殊的I/O控制代碼，它不在設(shè)備對(duì)象的特性中。宏CTL_CODE（在winioctl.h中定義）用來構(gòu)造控制代碼。這個(gè)宏的其中一個(gè)參數(shù)指明緩沖方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表顯示了這些方法和與之對(duì)應(yīng)的能獲得輸入緩沖與輸出緩沖的KIrp中的成員函數(shù)：Method Input Buffer Parameter OUTPUT Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代碼指明METHOD_BUFFERED，系統(tǒng)分配一個(gè)單一的緩沖來作為輸入與輸出。驅(qū)動(dòng)程序必須在向輸出緩沖放數(shù)據(jù)之前拷貝輸入數(shù)據(jù)。驅(qū)動(dòng)程序通過調(diào)用KIrp::IoctlBuffer獲得緩沖地址。在完成時(shí)，I/O管理器從系統(tǒng)緩沖拷貝數(shù)據(jù)到提供給Ring 3級(jí)調(diào)用者使用的緩沖中。驅(qū)動(dòng)程序必須在結(jié)束前存儲(chǔ)拷貝到IRP的Information成員中的數(shù)據(jù)個(gè)數(shù)。如果控制代碼不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，則DeviceIoControl的參數(shù)呈現(xiàn)不同的含義。參數(shù)InputBuffer被拷貝到一個(gè)系統(tǒng)緩沖，這個(gè)緩沖驅(qū)動(dòng)程序可以通過調(diào)用KIrp::IoctlBuffer。參數(shù)OUTPUTBuffer被映射到KMemory對(duì)象，驅(qū)動(dòng)程序?qū)@個(gè)對(duì)象的訪問通過調(diào)用KIrp::Mdl來實(shí)現(xiàn)。對(duì)于METHOD_OUT_DIRECT，調(diào)用者必須有對(duì)緩沖的寫訪問權(quán)限。注意，對(duì)METHOD_NEITHER，內(nèi)核只提供虛擬地址；它不會(huì)做映射來配置緩沖。虛擬地址只對(duì)調(diào)用進(jìn)程有效。這里是一個(gè)用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE來定義一個(gè)IOCTL代碼：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)現(xiàn)在使用一個(gè)DeviceIoControl調(diào)用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，這里放的是包含有執(zhí)行操作命令的字符串指針 0, FirmwareRev, //這里是OUTPUT串指針，存放從驅(qū)動(dòng)程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果輸出緩沖足夠大，設(shè)備拷貝串到里面并將拷貝的資結(jié)束設(shè)置到FirmwareRevSize中。在驅(qū)動(dòng)程序中，代碼看起來如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOUTPUTBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
標(biāo)簽： 驅(qū)動(dòng)程序 應(yīng)用程序 接口
上傳時(shí)間： 2013-10-17
上傳用戶：gai928943
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an OUTPUT, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog OUTPUT, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上傳時(shí)間： 2013-10-22
上傳用戶：taiyang250072
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its OUTPUT clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO OUTPUT is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2013-10-15
上傳用戶：euroford
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single OUTPUT video stream. The OUTPUT of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding OUTPUT.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-10-24
上傳用戶：bvdragon
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the OUTPUT data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) receivers use an external Sallen-Key datafilter and a data slicer to generate the baseband digital OUTPUT. This tutorial describes the ISM-RF Baseband Calculator,which can be used to calculate the filter capacitor values and the data slicer RC components, while providing a visualexample of the baseband signals.
上傳時(shí)間： 2013-11-04
上傳用戶：jkhjkh1982
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/OUTPUT (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時(shí)間： 2013-10-26
上傳用戶：yuzsu
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