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Proteus中文入門基礎(chǔ)教程
目 錄
第一章 概述... 2
一、進(jìn)入Proteus ISIS. 2
二、工作界面... 3
三、基本操作... 3
圖形編輯窗口... 3
預(yù)覽窗口（The OVERVIEW Window）... 4
對象選擇器窗口... 5
圖形編輯的基本操作... 5
參考1. 10
參考2作原理圖仿真調(diào)試... 12
四、實例一... 16
電路圖的繪制... 17
KeilC與Proteus連接調(diào)試... 26
五、實例二... 30
使用元件工具箱... 30
使用狀態(tài)信息條... 30
使用對話框... 30
使用仿真信息窗口... 30
關(guān)閉Proteus ISIS. 30
四、菜單命令簡述... 31
主窗口菜單... 31
表格輸出窗口(Table)菜單... 33
方格輸出窗口(Grid)菜單... 33
Smith圓圖輸出窗口(Smith)菜單... 33
直方圖輸出窗口(Histogram)菜單... 33
第二章 基于51的PID爐溫度調(diào)節(jié)器的硬件設(shè)計及仿真（未完成）... 34
標(biāo)簽：
Proteus
基礎(chǔ)教程
上傳時間：
2013-10-31
上傳用戶：hanli8870
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In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 OVERVIEW The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標(biāo)簽：
Bridge
Memory
Contr
MPC
上傳時間：
2013-10-08
上傳用戶：18711024007
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The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOVERVIEWÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
標(biāo)簽：
MPC
106
PCI
存儲器
上傳時間：
2013-11-04
上傳用戶：as275944189
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The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An OVERVIEW of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標(biāo)簽：
routines
slave
I2C
87L
上傳時間：
2013-11-19
上傳用戶：shirleyYim
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MCSÉ-51 Programmer's Guide and Instruction Set
The information presented in this chapter is collected from the MCSÉ-51 Architectural OVERVIEW and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
標(biāo)簽：
Program
Eacute
MCS
51
上傳時間：
2013-11-13
上傳用戶：hj_18
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winCE msdn講座 XP Embedded Now and the future
Windows XP Embedded Developmentand Deployment Model OVERVIEWWindows XP Embedded Component ModelWindows XP Embedded Studio Tools
Microsoft WindowsXP Embedded Product Highlights
Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
標(biāo)簽：
winCE
msdn
講座
上傳時間：
2013-10-31
上傳用戶：jrsoft
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This OVERVIEW guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2 shows the peripherals used by each device. Section 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.
標(biāo)簽：
281x
Dsp
281
外設(shè)
上傳時間：
2013-11-21
上傳用戶：HGH77P99
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This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an OVERVIEW of theadditional operations supported by XC9500/XL/XV CPLDs for in-system programming.
標(biāo)簽：
xapp
9500
JTAG
069
上傳時間：
2013-11-15
上傳用戶：fengweihao158@163.com
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Xilinx Next Generation 28 nm FPGA Technology OVERVIEW
Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
標(biāo)簽：
Xilinx
FPGA
312
WP
上傳時間：
2014-12-28
上傳用戶：zhang97080564
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This document provides an OVERVIEW of the MPC8313E PowerQUICC™II Pro processor features, including a block diagram showing the major functional components.
標(biāo)簽：
PowerQUICC
8313E
8313
MPC
上傳時間：
2013-11-20
上傳用戶：myworkpost
