On-line MCMC Bayesian Model Selection
This demo demonstrates how to use the sequential Monte Carlo algorithm with reversible jump MCMC steps to perform model selection in neural networks. We treat both the model dimension (number of neurons) and model parameters as unknowns. The derivation and details are presented in: Christophe Andrieu, Nando de Freitas and Arnaud Doucet. Sequential Bayesian Estimation and Model Selection Applied to Neural Networks . Technical report CUED/F-INFENG/TR 341, Cambridge University Department of Engineering, June 1999. After downloading the file, type "tar -xf version2.tar" to uncompress it. This creates the directory version2 containing the required m files. Go to this directory, load matlab5 and type "smcdemo1". In the header of the demo file, one can select to monitor the simulation progress (with par.doPlot=1) and modify the simulation parameters.
This software is not designed or intended for use in On-line control
* of aircraft, air traffic, aircraft navigation or aircraft
* communications or in the design, construction, operation or
* maintenance of any nuclear facility. Licensee represents and
* warrants that it will not use or redistribute the Software for such
Mega16是一款采用先進RISC精簡指令，內置A/D的8位單片機，可支持低電壓聯機 Flash和EEPROM 寫入功能；同時還支持 Basic和C 等高級語言編程。用它設計電子時鐘不僅成本低，硬件簡單，而且很容易實現系統移植。介紹了如何利用AVR系列單片機Mega16及1602字符液晶來設計電子時鐘的方法，同時給出了相應的電路原理及部分語言程序。
Abstract:
?Mega16 is a high-performance, low power consumption, the use of advanced RISC concise instructions, built-in A/D 8-bit microcontrollers, the On-line support for low-voltage Flash, EEPROM write function. Except Mega16 also support the Basic, C, and other high-level language programming.The electronic clock which is deisgned by Mega16 is not only low-cost, simple hardware, but easy to achieve system migration.The design method of electrioic clock based on the AVR Mega16 and character LCD1602 is introduced in this paper,and the corresponding circuit electrionic and some language program are given.
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the On-line masterand the slave devices on the downstream I2C-bus.
