One-channel queuing system simulator (M/M/1) * Arrival and service times are random and distributed exponetially. * * The simulator is time-slice-driven, i.e. the system model is being * run at discrete time points, with constant increments deltaT. * At each such time moment, program checks if a new item arrival or * release has occurred during previus deltaT.
標(biāo)簽： One-channel distributed and simulator
上傳時(shí)間： 2014-01-15
上傳用戶：kr770906
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時(shí)間： 2013-12-25
上傳用戶：jkhjkh1982
The BTS5016SDA is a one channel high-side power switch in PG-TO252-5-11 package providing embedded protective functions. The power transistor is built by a N-channel vertical power MOSFET with charge pump. The design is based on Smart SIPMOS chip on chip technology. The BTS5016SDA has a current controlled input and offers a diagnostic feedback with load current sense and a defined fault signal in case of overload operation, overtemperature shutdown and/or short circuit shutdown.
上傳時(shí)間： 2019-03-27
上傳用戶：guaixiaolong
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
標(biāo)簽： channel 9547 mult PCA
上傳時(shí)間： 2014-12-28
上傳用戶：270189020
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽： channel 9548A 9548 PCA
上傳時(shí)間： 2013-10-13
上傳用戶：bakdesec
ili9320 datasheet. ILI9320 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit.
標(biāo)簽： 9320 datasheet one-chip crystal
上傳時(shí)間： 2014-11-21
上傳用戶：jiahao131
游戲開(kāi)發(fā)大全-game.programming.all.in.one
標(biāo)簽： programming game all one
上傳時(shí)間： 2013-06-30
上傳用戶：eeworm
基于FPGA的單總線(ONE-WIRE)協(xié)議的實(shí)現(xiàn)源代碼.
標(biāo)簽： ONE-WIRE FPGA 單總線 協(xié)議
上傳時(shí)間： 2013-08-30
上傳用戶：wyc199288
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
標(biāo)簽： 2channel 9540B 9540 mult
上傳時(shí)間： 2014-12-28
上傳用戶：nshark
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標(biāo)簽： 4channel multiple 9544A 9544
上傳時(shí)間： 2014-12-28
上傳用戶：潛水的三貢
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