<li id="uyyie"></li> <li id="uyyie"></li> 針對目前使用的RS232接口數字化B超鍵盤存在PC主機啟動時不能設置BIOS，提出一種PS2鍵盤的設計方法。基于W78E052D單片機，采用8通道串行A/D轉換器設計了8個TGC電位器信息采集電路，電位器位置信息以鍵盤掃描碼序列形式發送，正交編碼器信號通過XC9536XL轉換為單片機可接收的中斷信號，軟件接收到中斷信息后等效處理成按鍵。結果表明，在滿足開機可設置BIOS同時，又可實現超聲特有功能，不需要專門設計驅動程序，接口簡單，成本低。 Abstract: Aiming at the problem of the digital ultrasonic diagnostic imaging system keyboard with RS232 interface currently used couldn?蒺t set the BIOS when the PC boot， this paper proposed a design method of PS2 keyboards. Based on W78E052D microcontroller，designed eight TGC potentiometers information acquisition circuit with 8-channel serial A/D converter， potentiometer position information sent out with keyboard scan code sequentially.The control circuit based on XC9536 CPLD is used for converting the mechanical actions of the encoders into the signals that can be identified by the MCU， software received interrupt information and equivalently treatmented as key. The results show that the BIOS can be set to meet the boot， ultrasound specific functionality can be achieved at the same time， it does not require specially designed driver，the interface is simple and low cost.
上傳時間： 2013-10-10
上傳用戶：asdfasdfd
SDRAM的原理和時序 SDRAM內存模組與基本結構 我們平時看到的SDRAM都是以模組形式出現，為什么要做成這種形式呢？這首先要接觸到兩個概念：物理Bank與芯片位寬。1、 物理Bank 傳統內存系統為了保證CPU的正常工作，必須一次傳輸完CPU在一個傳輸周期內所需要的數據。而CPU在一個傳輸周期能接受的數 據容量就是CPU數據總線的位寬，單位是bit（位）。當時控制內存與CPU之間數據交換的北橋芯片也因此將內存總線的數據位寬 等同于CPU數據總線的位寬，而這個位寬就稱之為物理Bank（Physical Bank，下文簡稱P-Bank）的位寬。所以，那時的內存必須要組織成P-Bank來與CPU打交道。資格稍老的玩家應該還記 得Pentium剛上市時，需要兩條72pin的SIMM才能啟動，因為一條72pin -SIMM只能提供32bit的位寬，不能滿足Pentium的64bit數據總線的需要。直到168pin-SDRAM DIMM上市后，才可以使用一條內存開機。不過要強調一點，P-Bank是SDRAM及以前傳統內存家族的特有概念，RDRAM中將以通道（Channel）取代，而對 于像Intel E7500那樣的并發式多通道DDR系統，傳統的P-Bank概念也不適用。2、 芯片位寬 上文已經講到SDRAM內存系統必須要組成一個P-Bank的位寬，才能使CPU正常工作，那么這個P-Bank位寬怎么得到呢 ？這就涉及到了內存芯片的結構。 每個內存芯片也有自己的位寬，即每個傳輸周期能提供的數據量。理論上，完全可以做出一個位寬為64bit的芯片來滿足P-Ban k的需要，但這對技術的要求很高，在成本和實用性方面也都處于劣勢。所以芯片的位寬一般都較小。臺式機市場所用的SDRAM芯片 位寬最高也就是16bit，常見的則是8bit。這樣，為了組成P-Bank所需的位寬，就需要多顆芯片并聯工作。對于16bi t芯片，需要4顆（4×16bit=64bit）。對于8bit芯片，則就需要8顆了。以上就是芯片位寬、芯片數量與P-Bank的關系。P-Bank其實就是一組內存芯片的集合，這個集合的容量不限，但這個集合的 總位寬必須與CPU數據位寬相符。隨著計算機應用的發展，
上傳時間： 2013-11-04
上傳用戶：zhuimenghuadie
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標簽： 4channel transla level 9519
上傳時間： 2013-11-19
上傳用戶：jisiwole
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register. Two interrupt inputs, INT0 and INT1, one for each of theSCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as anAND of the two interrupt inputs, is provided.
上傳時間： 2013-12-07
上傳用戶：europa_lin
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上傳時間： 2014-11-22
上傳用戶：xcy122677
The PCA9546A is a quad bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.
上傳時間： 2013-11-16
上傳用戶：cc1915
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
上傳時間： 2014-12-28
上傳用戶：270189020
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上傳時間： 2013-10-13
上傳用戶：bakdesec
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時間： 2013-10-11
上傳用戶：dianxin61
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-23
上傳用戶：leyesome
