These routines transmit and receive serial data using two general
* I/O PINS, in 8 bit, No parity, 1 stop bit format. They are useful
* for performing serial I/O on 8051 derivatives not having an
* internal UART, or for implementing a second serial channel.
When the P89LPC90x is in programming mode all PINS that are not used for programming are tri-stated. During
programming mode the reset pin has a weak pull-up resistor.
富士通單片機(jī)MB902420系列
extINT Project:
All external Interrupt-PINS INT0 .. INT7 will be enabled.
A falling edge on INTx will toggle PDR4_P4x
in order to toggle the LEDx of the Flash-CAN-100P Board
e.g. falling edge on INT3 will result in LED D3 will toggleP47..P40 (UserLEDs of FlashCan100P)
and will send out again as byte-packages to ID#2
Receive-Buffer #1 : basic can
Transmit-Buffer #6 : full-can ID #2
Device PINS that are not connected to a specific peripheral function are controlled by the
GPIO registers. PINS may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simu
中文
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input PINS: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output PINS: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input PINS: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output PINS: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
