摘 要 瞬態(tài)仿真領(lǐng)域的許多工作需要獲得可視化數(shù)據(jù), 仿真電路不能將輸出參數(shù)繪制成圖形時研究工作將受到很大影響. 而權(quán)威電路仿真軟件PSpice 在這個方面不盡如人意. 本文提出了一種有效的解決辦法: 通過MATLAB 編程搭建一個PSpice 與MATLAB 的數(shù)據(jù)接口,使PSpice輸出數(shù)據(jù)文件可以導(dǎo)入到MATLAB中繪制圖形. 這令我們能夠很方便地獲得數(shù)據(jù)的規(guī)律以有效地分析仿真結(jié)果, 這項技術(shù)對于教學和工程實踐都有比較實際的幫助.關(guān)鍵詞: 瞬態(tài)仿真 仿真程序 PSpice MATLAB 可視化數(shù)據(jù)The Data Transfer from Pspice to MATLABWu hao Ning yuanzhong Liang yingAbstract Many works in the area of transient simulation has shown how a emulator such asPSpice can be interfaced to an control analysis package such as MATLAB to get viewdata. Thepaper describes how such interfaces can be made using the MATLAB programming. The PLATFORMas a typical PLATFORM will solve the problem that PSpice software sometimes can not draw the datato a picture. It can make us find the rule from numerous data very expediently, so we can analyzethe outcome of the simulation. And it also can be used in the field of education.Keywords Transient Simulation Emulator PSpice MATLAB Viewdata1 引言科學研究和工程應(yīng)用常需要進行電路仿真 PSpice可進行直流 交流 瞬態(tài)等基本電路特性分析 也可進行蒙托卡諾 MC 統(tǒng)計分析 最壞情況 Wcase 分析 優(yōu)化設(shè)計等復(fù)雜電路特性分析 它是國際上仿真電路的權(quán)威軟件 而MATLAB的主要特點有 高效方便的矩陣和數(shù)組運算 編程效率高 結(jié)構(gòu)化面向?qū)ο?方便的繪圖功能 用戶使用方便 工具箱功能強大 兩者各有著重點 兩種軟件結(jié)合應(yīng)用 對研究工作有很重要的意義香港理工大學Y. S. LEE 等人首先將PSpice和MATLAB結(jié)合 開發(fā)了電力電子電路優(yōu)化用的CAD 程序MATSPICE[6] 將兩者相結(jié)合的關(guān)鍵在于 如何用MATLAB 獲取PSpice的仿真數(shù)據(jù) 對此參考文獻 6 里沒有詳細敘述 本文著重說明用MATLAB 讀取PSpice仿真數(shù)據(jù)的具體方法本論文利用MATLAB對PSpice仿真出的數(shù)據(jù)處理繪制出后者無法得到或是效果不好的仿真圖形 下面就兩者結(jié)合使用的例子 進行具體說明
標簽： MATLAB PSpice 數(shù)據(jù) 接口技術(shù)
上傳時間： 2013-10-20
上傳用戶：wuchunzhong
本文著重介紹了 Xilinx PLATFORM Flash PROM 如何幫助系統(tǒng)和電路板設(shè)計人員簡化 FPGA 配置設(shè)計。用于配置 FPGA 的可選解決方案有很多，但它們通常都需要大量的前期設(shè)計工作和時間。PLATFORM Flash 是為配置 Xilinx FPGA 專門設(shè)計的一款包括硬件和軟件支持在內(nèi)的整體解決方案。
上傳時間： 2013-11-03
上傳用戶：zhangchu0807
Abstract: This reference design explains how to power the Xilinx Zynq Extensible Processing PLATFORM (EPP) and peripheral ICs using
上傳時間： 2014-01-21
上傳用戶：haohao
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and PLATFORM Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時間： 2013-11-11
上傳用戶：zhouli
WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing PLATFORM is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing PLATFORM takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing PLATFORM.
上傳時間： 2013-10-22
上傳用戶：685
The Xilinx Zynq-7000 Extensible Processing PLATFORM (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible PLATFORM to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間： 2013-11-01
上傳用戶：dingdingcandy
本文著重介紹了 Xilinx PLATFORM Flash PROM 如何幫助系統(tǒng)和電路板設(shè)計人員簡化 FPGA 配置設(shè)計。用于配置 FPGA 的可選解決方案有很多，但它們通常都需要大量的前期設(shè)計工作和時間。PLATFORM Flash 是為配置 Xilinx FPGA 專門設(shè)計的一款包括硬件和軟件支持在內(nèi)的整體解決方案。
上傳時間： 2013-11-04
上傳用戶：ifree2016
針對嵌入式機器視覺系統(tǒng)向獨立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機。基于對智能相機體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對國內(nèi)外的幾款智能相機進行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計可以實現(xiàn)脫離PC運行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware PLATFORM based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
上傳時間： 2013-10-24
上傳用戶：bvdragon
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software PLATFORM,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2014-01-13
上傳用戶：qoovoop
ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf PLATFORM: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
上傳時間： 2013-11-24
上傳用戶：31633073
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