本文著重介紹了 Xilinx PLATFORM Flash PROM 如何幫助系統(tǒng)和電路板設(shè)計(jì)人員簡化 FPGA 配置設(shè)計(jì)。用于配置 FPGA 的可選解決方案有很多，但它們通常都需要大量的前期設(shè)計(jì)工作和時(shí)間。PLATFORM Flash 是為配置 Xilinx FPGA 專門設(shè)計(jì)的一款包括硬件和軟件支持在內(nèi)的整體解決方案。
上傳時(shí)間： 2014-01-09
上傳用戶：時(shí)代電子小智
面向Eclips的Nios II軟件構(gòu)建工具手冊 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development PLATFORM that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時(shí)間： 2013-11-02
上傳用戶：瓦力瓦力hong
Abstract: This reference design explains how to power the Xilinx Zynq Extensible Processing PLATFORM (EPP) and peripheral ICs using
標(biāo)簽： Xilinx Zynq EPP 擴(kuò)展式
上傳時(shí)間： 2013-10-13
上傳用戶：peterli123456
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and PLATFORM Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時(shí)間： 2013-10-09
上傳用戶：guojin_0704
WP369可擴(kuò)展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing PLATFORM is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing PLATFORM takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing PLATFORM.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺
上傳時(shí)間： 2013-10-18
上傳用戶：cursor
The Xilinx Zynq-7000 Extensible Processing PLATFORM (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible PLATFORM to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-10-09
上傳用戶：evil
本文著重介紹了 Xilinx PLATFORM Flash PROM 如何幫助系統(tǒng)和電路板設(shè)計(jì)人員簡化 FPGA 配置設(shè)計(jì)。用于配置 FPGA 的可選解決方案有很多，但它們通常都需要大量的前期設(shè)計(jì)工作和時(shí)間。PLATFORM Flash 是為配置 Xilinx FPGA 專門設(shè)計(jì)的一款包括硬件和軟件支持在內(nèi)的整體解決方案。
上傳時(shí)間： 2013-11-02
上傳用戶：lixinxiang
針對嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對國內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware PLATFORM based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-11-14
上傳用戶：無聊來刷下
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software PLATFORM,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf PLATFORM: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VHDL ZBT
上傳時(shí)間： 2013-10-25
上傳用戶：peterli123456
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