Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any effect on system operation to rendering the system completely non-functional. This application note provides the reader with a clear understanding of jitter in high-speed systems. It introduces the reader to various kinds of jitter in high-speed systems, their causes and their effects, and methods of reducing jitter. This application note will concentrate on jitter in PLL-based frequency synthesizers.
標(biāo)簽： extremely PLL-based important drivers
上傳時間： 2014-11-25
上傳用戶：asddsd
Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides a set of recommendations to optimize usage of Cypress clock devices in a system. The application note begins with recommended termination techniques for clock generators. Subsequently, power supply filtering and bypassing is discussed. Finally, the application note provides some recommendations on board layout.
標(biāo)簽： Semiconductor application generators PLL-based
上傳時間： 2013-12-20
上傳用戶：水中浮云
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) products use crystal oscillators to generate areference for the phase-locked loop (PLL)-based local oscillator (LO). This tutorial provides a basic description of theISM-RF Crystal Calculator, which can be used to calculate various impacts on crystal frequency accuracy and startupmargin for such an LO.
上傳時間： 2013-11-15
上傳用戶：JasonC
PLL電路
上傳時間： 2013-08-01
上傳用戶：eeworm
專輯類-可編程邏輯器件相關(guān)專輯-96冊-1.77G PLL電路-3.8M.zip
上傳時間： 2013-06-09
上傳用戶：bcjtao
鎖相環(huán)PLL原理與應(yīng)用教程，講的通俗易懂
上傳時間： 2013-07-12
上傳用戶：lijinchuan
PLL芯片MB1504編程參考（匯編）PLL芯片MB1504編程參考（匯編）PLL芯片MB1504編程參考（匯編）PLL芯片MB1504編程參考（匯編）
上傳時間： 2013-07-12
上傳用戶：wyaqy
資料->【E】光盤論文->【E1】斯坦福博士論文->02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf
標(biāo)簽： Location-Based Applications Java-Based Framework
上傳時間： 2013-07-02
上傳用戶：亞亞娟娟123
FPGA-based high-order FIR filter design
標(biāo)簽： FPGA-based high-order filter design
上傳時間： 2013-08-06
上傳用戶：sssnaxie
基于FPGA和PLL的函數(shù)信號發(fā)生器時鐘部分的實(shí)現(xiàn)
標(biāo)簽： FPGA PLL 函數(shù)信號發(fā)生器 時鐘
上傳時間： 2013-08-08
上傳用戶：xzt
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