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POST-linker

  • 西門子公司的DP/PA linker的gsd文件

    西門子公司的DP/PA linker的gsd文件,通過對該gsd研究,可以對linker的工作原理有一定認(rèn)識

    標(biāo)簽: linker gsd DP PA

    上傳時(shí)間: 2013-12-17

    上傳用戶:邶刖

  • 基于ARM的嵌入式Web服務(wù)器的研究與實(shí)現(xiàn)

    近年來,隨著嵌入式系統(tǒng)的快速發(fā)展,越來越多的嵌入式設(shè)備被用于工業(yè)控制、智能家居等領(lǐng)域。同時(shí)伴隨著網(wǎng)絡(luò)技術(shù)的發(fā)展,嵌入式設(shè)備通過網(wǎng)絡(luò)接入局域網(wǎng)或者Internet已經(jīng)逐步成為發(fā)展的趨勢。通過在嵌入式設(shè)備中內(nèi)置Web服務(wù)器,用戶可以在任何一臺聯(lián)網(wǎng)的計(jì)算機(jī)上通過瀏覽器來獲取設(shè)備的信息,用戶還可以通過網(wǎng)絡(luò)對設(shè)備進(jìn)行配置和管理。因此研究和開發(fā)嵌入式Web服務(wù)器具有重要的實(shí)際意義和應(yīng)用價(jià)值。 本文在S3C44BOX開發(fā)板上使用μClinux操作系統(tǒng)作為開發(fā)平臺,開發(fā)并實(shí)現(xiàn)了嵌入式Web服務(wù)器。文中提出了2種實(shí)現(xiàn)方案,一種是基于boa的嵌入式Web服務(wù)器,所做的主要工作是boa在gClinux中的移植和CGI的編寫,在此基礎(chǔ)上實(shí)現(xiàn)了動、靜態(tài)頁面的生成和簡單的控制功能。另一種方案是基于HTTP協(xié)議和socket編程所開發(fā)的嵌入式Web服務(wù)器,在此方案中實(shí)現(xiàn)了HTTP協(xié)議的GET和POST請求方式,能夠生成簡單的動態(tài)頁面,實(shí)現(xiàn)了歷史數(shù)據(jù)的保存功能,還能夠根據(jù)用戶在瀏覽器端的請求進(jìn)行相應(yīng)的控制和管理。 論文首先對嵌入式Web服務(wù)器的體系結(jié)構(gòu)進(jìn)行了分析,然后介紹了S3C44BOX硬件開發(fā)平臺,并分析了bootloader的基本原理和實(shí)現(xiàn)過程。隨后對μClinux操作系統(tǒng)的特點(diǎn)和網(wǎng)卡驅(qū)動程序進(jìn)行了分析,并著重介紹了μClinux的移植過程。在第五章,論文詳細(xì)分析了TCP/IP和HTTP的原理和工作機(jī)制,并介紹了Web服務(wù)器中CGI的工作原理,最后分析了boa服務(wù)器的移植和CGI程序的編寫以及Web服務(wù)器的測試等。在第六章,在HTTP協(xié)議分析和網(wǎng)絡(luò)編程的基礎(chǔ)上,提出了嵌入式Web服務(wù)器的設(shè)計(jì)思想、程序流程圖,重點(diǎn)分析了Web服務(wù)器主程序流程、動態(tài)頁面的生成、歷史數(shù)據(jù)查詢的實(shí)現(xiàn)等,也分析了Web服務(wù)器中各種控制功能的實(shí)現(xiàn)流程,最后給出了Web服務(wù)器的測試結(jié)果。

    標(biāo)簽: ARM Web 嵌入式 服務(wù)器

    上傳時(shí)間: 2013-05-17

    上傳用戶:ice_qi

  • 數(shù)字電源學(xué)習(xí)資料

    Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission.

    標(biāo)簽: 數(shù)字電源

    上傳時(shí)間: 2013-10-16

    上傳用戶:dddddd

  • FET430PIF自制資料

    The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is included in our FET tools, but sold without the development board. This interface uses a Parallel PC Port to communicate to the Debugger Software (IAR Kickstart software included) running on the PC. The interface uses the standard 14 pin header to communicate to the MSP430 device using the standard JTAG protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required. The tool has an integrated software environment and connects directly to the PC which greatly simplifies the set-up and use of the tool. The flash development tool supports development with all MSP430 flash parts. Features MSP430 debugging interface to connect a MSP430-Flash-device to a Parallel port on a PC Supports JTAG debug protocol (NO support for Spy-Bi-Wire (2-wire JTAG) debug protocol, Spy-Bi-Wire (2-wire JTAG) is supported by MSP-FET430UIF) Parallel Port cable and a 14-conductor target cable Full documentation on CD ROM Integrated IAR Kickstart user interface which includes: Assembler Linker Limulator Source-level debugger Limited C-compiler Technical specifications: Backwardly compatable with existing FET tool boards.

    標(biāo)簽: FET 430 PIF

    上傳時(shí)間: 2013-10-26

    上傳用戶:fengweihao158@163.com

  • 怎樣寫testbench-xilinx

    怎樣寫testbench-xilinx  在ISE 環(huán)境中, 當(dāng)前資源操作窗顯示了資源管理窗口中選中的資源文件能進(jìn)行的相關(guān)操作。在資源管理窗口選中了 testbench 文件后,在當(dāng)前資源操作窗顯示的 ModelSim Simulator 中顯示了4種能進(jìn)行的模擬操作,分別是:Simulator Behavioral Model(功能仿真)、Simulator Post-translate VHDL Model(翻譯后仿真)、Simulator Post-Map VHDL Model(映射后仿真)、Simulator Post-Place & Route VHDL Model(布局布線后仿真) 。如

    標(biāo)簽: testbench-xilinx

    上傳時(shí)間: 2013-11-14

    上傳用戶:467368609

  • Virtex-6 FPGA PCB設(shè)計(jì)手冊

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    標(biāo)簽: Virtex FPGA PCB 設(shè)計(jì)手冊

    上傳時(shí)間: 2014-01-13

    上傳用戶:竺羽翎2222

  • CPLD庫指南

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.  

    標(biāo)簽: CPLD

    上傳時(shí)間: 2013-10-22

    上傳用戶:李哈哈哈

  • Virtex-6 FPGA PCB設(shè)計(jì)手冊

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    標(biāo)簽: Virtex FPGA PCB 設(shè)計(jì)手冊

    上傳時(shí)間: 2013-11-11

    上傳用戶:zwei41

  • CPLD庫指南

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.  

    標(biāo)簽: CPLD

    上傳時(shí)間: 2014-12-05

    上傳用戶:qazxsw

  • Firepass - 一種隧道技術(shù)工具

    Firepass - 一種隧道技術(shù)工具,通過它可以避開防火墻的規(guī)則約束,將數(shù)據(jù)流封裝在合法的HTTP POST請求中。任何基于TCP/UDP協(xié)議的子協(xié)議可以通過它來穿越HTTP代理服務(wù)器對HTTP協(xié)議的嚴(yán)格審查。到目前為止,客戶端和服務(wù)器端僅用PERL語言編寫。服務(wù)器端作為一個(gè)CGI腳本運(yùn)行在WEB服務(wù)器上。Firepass的主要特點(diǎn)是用戶可以在外網(wǎng)使用幾種方法安裝服務(wù)器端腳本。用戶無需在外網(wǎng)計(jì)算機(jī)上幫定任何端口。當(dāng)服務(wù)端腳本被置于企業(yè)WEB服務(wù)器上,客戶端腳本從外部網(wǎng)絡(luò)和它通信時(shí),F(xiàn)irepass也可適用于反彈作業(yè)。

    標(biāo)簽: Firepass 隧道

    上傳時(shí)間: 2013-12-25

    上傳用戶:D&L37

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