AI :Auto-Insertion 自動插件 AQL :acceptable quality level 允收水準 ATE :automatic test equipment 自動測試 ATM :atmosphere 氣壓 BGA :ball grid array 球形矩陣
上傳時間： 2013-11-20
上傳用戶：haoxiyizhong
Aspen Plus介紹 (物性數(shù)據(jù)庫) · Aspen Plus ---生產(chǎn)裝置設(shè)計、穩(wěn)態(tài)模擬和優(yōu)化的大型通用流程模擬系統(tǒng) · Aspen Plus是大型通用流程模擬系統(tǒng)，源于美國能源部七十年代后期在麻省理工學(xué)院(MIT)組織的會 戰(zhàn)，開發(fā)新型第三代流程模擬軟件。該項目稱為“過程工程的先進系統(tǒng)”(Advanced System for Process Engineering，簡稱ASPEN),并于1981年底完成。1982年為了將其商品化，成立了AspenTech公司，并稱之為Aspen Plus。該軟件經(jīng)過20多年來不斷地改進、擴充和提高，已先后推出了十多個版本，成為舉世公認的標準大型流程模擬軟件，應(yīng)用案例數(shù)以百萬計。全球各大化工、石化、煉油等過程工業(yè)制造企業(yè)及著名的工程公司都是Aspen Plus的用戶。 它以嚴格的機理模型和先進的技術(shù)贏得廣大用戶的信賴，它具有以下特性： 1. ASPEN PLUS有一個公認的跟蹤記錄，在一個工藝過程的制造的整個生命周期中提供巨大的經(jīng)濟效益，制造生命周期包括從研究與開發(fā)經(jīng)過工程到生產(chǎn)。 2. ASPEN PLUS使用最新的軟件工程技術(shù)通過它的Microsoft Windows圖形界面和交互式客戶-服務(wù)器模擬結(jié)構(gòu)使得工程生產(chǎn)力最大。 3. ASPEN PLUS擁有精確模擬范圍廣泛的實際應(yīng)用所需的工程能力， 這些實際應(yīng)用包括從煉油到非理想化學(xué)系統(tǒng)到含電解質(zhì)和固體的工藝過程。 4. ASPEN PLUS是AspenTech的集成聰明制造系統(tǒng)技術(shù)的一個核心部分， 該技術(shù)能在你公司的整個過程工程基本設(shè)施范圍內(nèi)捕獲過程專業(yè)知識并充分利用。 在實際應(yīng)用中，ASPEN PLUS可以幫助工程師解決快速閃蒸計算、設(shè)計一個新的工藝過程、查找一個原油加工裝置的故障或者優(yōu)化一個乙烯全裝置的操作等工程和操作的關(guān)鍵問。
上傳時間： 2013-11-16
上傳用戶：我干你啊
附件是一款PCB阻抗匹配計算工具，點擊CITS25.exe直接打開使用，無需安裝。附件還帶有PCB連板的一些計算方法，連板的排法和PCB聯(lián)板的設(shè)計驗驗。 PCB設(shè)計的經(jīng)驗建議: 1.一般連板長寬比率為1：1~2.5：1,同時注意For FuJi Machine:a.最大進板尺寸為:450*350mm, 2.針對有金手指的部分,板邊處需作掏空處理,建議不作為連板的部位. 3.連板方向以同一方向為優(yōu)先,考量對稱防呆,特殊情況另作處理. 4.連板掏空長度超過板長度的1/2時,需加補強邊. 5.陰陽板的設(shè)計需作特殊考量. 6.工藝邊需根據(jù)實際需要作設(shè)計調(diào)整,軌道邊一般不少於6mm,實際中需考量板邊零件的排布,軌道設(shè)備正常卡壓距離為不少於3mm,及符合實際要求下的連板經(jīng)濟性. 7.FIDUCIAL MARK或稱光學(xué)定位點,一般設(shè)計在對角處,為2個或4個,同時MARK點面需平整,無氧化,脫落現(xiàn)象;定位孔設(shè)計在板邊,為對稱設(shè)計,一般為4個,直徑為3mm,公差為±0.01inch. 8.V-cut深度需根據(jù)連板大小及基板板厚考量,角度建議為不少於45°. 9.連板設(shè)計的同時,需基於基板的分板方式考量<人工(治具)還是使用分板設(shè)備>. 10.使用針孔(郵票孔)聯(lián)接：需請考慮斷裂后的毛刺,及是否影響COB工序的Bonding機上的夾具穩(wěn)定工作,還應(yīng)考慮是否有無影響插件過軌道,及是否影響裝配組裝.
上傳時間： 2013-10-15
上傳用戶：3294322651
封裝規(guī)格大全，實用的的計數(shù)資料！
上傳時間： 2014-01-04
上傳用戶：kinochen
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標簽： FPGA 安全系統(tǒng)
上傳時間： 2013-11-14
上傳用戶：zoudejile
使用Nios II軟件構(gòu)建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.
上傳時間： 2013-10-12
上傳用戶：china97wan
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
上傳時間： 2013-11-16
上傳用戶：qingdou
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時間： 2013-11-03
上傳用戶：ysystc670
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時間： 2013-12-07
上傳用戶：bruce
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