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基于單DSP的VoIP模擬電話適配器研究與實現(xiàn):提出和實現(xiàn)了一種新穎的基于單個通用數(shù)字信號處理器(DSP)的VoIP模擬電話適配器方案。DSP的I/O和存儲資源非常有限，通常適于運算密集型應用，不適宜控制密集型應用[5]。該系統(tǒng)高效利用單DSP的I/O和片內外存儲器資源，采用μC/OS-II嵌入式實時操作系統(tǒng)，支持SIP和TCP-UDP/IP協(xié)議，通過LAN或者寬帶接入，使普通電話機成為Internet終端，實現(xiàn)IP電話。該系統(tǒng)軟硬件結構緊湊高效，運行穩(wěn)定，成本低，具有廣闊的應用前景。關鍵詞：模擬電話適配器；IP電話；數(shù)字信號處理器；μC/OS-II
【Abstract】This paper presents a VoIP ATA solution based on a single digital signal PROCESSOR (DSP). DSPs are suitable for arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal PROCESSOR (DSP); μC/OS-II
Research and Implementation of VoIPATA Based on Single DSP
標簽：
VoIP
DSP
模擬電話
適配器
上傳時間：
2013-11-20
上傳用戶：Wwill
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本章將介紹μ’nSP™系列單片機的應用領域，具體講述SPCE061A單片機在通訊、語音領域里的應用，并詳細給出了有關系統(tǒng)的電路原理圖、程序流程圖以及程序代碼，供讀者參考。
μ’nSP™家族產品具有電源電壓范圍和工作速率范圍較寬、集成度高、性能價格比高以及功耗低等特點，故其有非常廣泛的應用領域。μ’nSP™家族系列產品，涵蓋了非常廣泛的應用。包括：發(fā)音與語音識別的微控制器（SPCE系列）、通信來電辯識應用的微控制器（SPT660x系列）、以及通用型微控制器等等，主要體現(xiàn)在以下幾個方面： 用于數(shù)字信號處理 用于開發(fā)研制便攜式移動終端 用于開發(fā)嵌入式計算機應用系統(tǒng)
用于數(shù)字信號處理1． 數(shù)字濾波器 (Digital Filter)數(shù)字濾波器是一種計算處理或算法。借助于此，可以將輸入的一種數(shù)字信號或序列變換為另一種序列輸出。數(shù)字濾波器已被廣泛地應用于數(shù)字語音、數(shù)字圖像處理以及模式識別和頻譜分析。數(shù)字信號處理器（DSP，Digital Signal PROCESSOR）的作用是通過一系列數(shù)字來表示信號及其信息，并借助數(shù)字計算方法變換和處理這些信號。為了構成DSP，必須有一種部件能夠快速地完成兩個數(shù)值的乘法運算并將乘積累加于寄存器。“快速”意味著乘和累加（MAC，Multiply & ACcumulate）較高的運算速度。若以16位數(shù)值進行乘和累加，其結果應為32位。顯然，μ’nSP™的硬件結構與其指令系統(tǒng)的結合足以構成DSP應用的硬件MAC單元，因而很適用于一些DSP方面的應用。
標簽：
nSP
單片機應用
開發(fā)技術
上傳時間：
2014-01-26
上傳用戶：qb1993225
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In this document, the term Ô60xÕ is used to denote a 32-bit microPROCESSOR from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microPROCESSORs. Note that this does not include the PowerPC 602ª microPROCESSOR which has a multiplexed address/data bus. 60x PROCESSORs implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x PROCESSOR, a secondary (L2) cache or additional (up to four total) 60x PROCESSORs, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標簽：
Bridge
Memory
Contr
MPC
上傳時間：
2013-10-08
上傳用戶：18711024007
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Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control PROCESSOR (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
標簽：
Exter
easy
work
with
上傳時間：
2013-10-27
上傳用戶：zhangyigenius
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The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as thePROCESSOR plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the PROCESSOR simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標簽：
routines
slave
I2C
87L
上傳時間：
2013-11-19
上傳用戶：shirleyYim
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I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andPROCESSOR-to-PROCESSOR communications.
標簽：
microcontro
Using
76X
LPC
上傳時間：
2013-12-30
上傳用戶：Artemis
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基于ADSP-BF561的數(shù)字攝像系統(tǒng)設計Design of Digital Video Camera System Based on Digital Signal PROCESSORADSP-BF561（浙江大學 信息與通信工程研究所，浙江 杭州 310027） 馬海杰, 劉云海摘要：介紹了基于ADI雙核的數(shù)字信號處理芯片ADSP-BF561 的數(shù)字攝像系統(tǒng)實現(xiàn)方案。系統(tǒng)包括硬件和軟件兩部分，硬件主要有ADSP-BF561及其外圍電路、音視頻模數(shù)/數(shù)模轉換、CF卡/微硬盤接口等部分。軟件主要有操作系統(tǒng)及音視頻編解碼算法等部分。關鍵詞：ADSP-BF561 ;數(shù)字攝像機;微硬盤;MPEG-4;A/D;D/A中圖分類號:TN948.41文獻標識碼:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal PROCESSOR ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A
標簽：
ADSP-BF
561
數(shù)字攝像
系統(tǒng)設計
上傳時間：
2013-11-10
上傳用戶：yl1140vista
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為了擴大監(jiān)控范圍，提高資源利用率，降低系統(tǒng)成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據(jù)行場信號由DSP和FPGA產生控制信號，控制多路視頻通道之間的切換，從而實現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實驗結果表明，該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實現(xiàn)視頻通道的切換。
Abstract:
To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus， it achieves to make a video PROCESSOR to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
標簽：
FPGA
DSP
視頻通道
切換控制
上傳時間：
2013-11-09
上傳用戶：不懂夜的黑
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在綜合分析諧波勵磁無刷同步發(fā)電機勵磁控制系統(tǒng)的基礎上,對其勵磁控制策略進行了研究,開發(fā)了一套基于DSP( TMS320F2812) 控制的新型柴油發(fā)電機勵磁控制系統(tǒng),該系統(tǒng)采用參數(shù)自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統(tǒng)仿真結果以及在1 臺25 kW 工頻柴油發(fā)電機上的試驗結果證明了該控制器具有較好的電壓調節(jié)特性,系統(tǒng)穩(wěn)態(tài)和暫態(tài)性能完全滿足發(fā)電機對勵磁系統(tǒng)的要求。關鍵詞:勵磁調節(jié);模糊PID 控制;數(shù)字信號處理器;交流采樣
Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal PROCESSOR (DSP) ;AC sampling
標簽：
DSP
柴油發(fā)電機
勵磁控制
系統(tǒng)研究
上傳時間：
2013-10-29
上傳用戶：fxf126@126.com
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This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither PROCESSOR nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標簽：
Spartan
XAPP
FPGA
098
上傳時間：
2014-08-16
上傳用戶：adada
