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Peripherals

  • XA-S3的IIC接口的驅動器軟件程序(C語言)

    The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful Peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip Peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.

    標簽: XA-S IIC C語言 接口

    上傳時間: 2013-11-10

    上傳用戶:liaofamous

  • 3.3v看門狗芯片

    The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding Peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.

    標簽: 3.3 看門狗 芯片

    上傳時間: 2013-10-22

    上傳用戶:taiyang250072

  • pk51下載 (8051單片機開發工具)

    PK51是為8051系列單片機所設計的開發工具,支持所有8051系列衍生產品,,支持帶擴展存儲器和擴展指令集(例如Dallas390/5240/400,Philips 51MX,Analog Devices MicroConverters)的新設備,以及支持很多公司的一流的設備和IP內核,比如Analog Devices, Atmel, Cypress Semiconductor, Dallas Semiconductor, Goal, Hynix, Infineon, Intel, NXP(founded by Philips), OKI, Silicon Labs,SMSC, STMicroeleectronics,Synopsis, TDK, Temic, Texas Instruments,Winbond等。通過PK51專業級開發工具,可以輕松地了解8051的On-chip Peripherals與及其它關鍵特性。    

    標簽: 8051 pk 51

    上傳時間: 2013-10-09

    上傳用戶:1109003457

  • Dsp281x外設資料

    This overview guide describes all the Peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2 shows the Peripherals used by each device. Section 3 provides descriptions of the Peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.

    標簽: 281x Dsp 281 外設

    上傳時間: 2013-11-21

    上傳用戶:HGH77P99

  • C51 V8 專業開發工具

    Keil C51 V8 專業開發工具(PK51)   PK51是為8051系列單片機所設計的開發工具,支持所有8051系列衍生產品,,支持帶擴展存儲器和擴展指令集(例如Dallas390/5240/400,Philips 51MX,Analog Devices MicroConverters)的新設備,以及支持很多公司的一流的設備和IP內核,比如Analog Devices, Atmel, Cypress Semiconductor, Dallas Semiconductor, Goal, Hynix, Infineon, Intel, NXP(founded by Philips), OKI, Silicon Labs,SMSC, STMicroeleectronics,Synopsis, TDK, Temic, Texas Instruments,Winbond等。 通過PK51專業級開發工具,可以輕松地了解8051的On-chip Peripherals與及其它關鍵特性。 The PK51專業級開發工具包括… l          μVision Ø         集成開發環境 Ø          調試器 Ø         軟件模擬器   l          Keil 8051擴展編譯工具 Ø         AX51宏匯編程序 Ø         ANSI C編譯工具 Ø         LX51 連接器 Ø         OHX51 Object-HEX 轉換器 l          Keil 8051編譯工具 Ø         A51宏匯編程序 Ø         C51 ANSI C編譯工具 Ø         BL51 代碼庫連接器 Ø         OHX51 Object-HEX 轉換器 Ø         OC51 集合目標轉換器   l          目標調試器 Ø         FlashMON51 目標監控器 Ø         MON51目標監控器 Ø         MON390 (Dallas 390)目標監控器 Ø         MONADI (Analog Devices 812)目標監控器 Ø         ISD51 在系統調試   l          RTX51微實時內核   你應該考慮PK51開發工具包,如果你… l          需要用8051系列單片機來開發 l          需要開發 Dallas 390 或者 Philips 51MX代碼 l          需要用C編寫代碼 l          需要一個軟件模擬器或是沒有硬件仿真器 l          需要在單芯片上基于小實時內核創建復雜的應用

    標簽: C51 V8 開發工具

    上傳時間: 2013-10-30

    上傳用戶:yy_cn

  • LPC1850 Cortex-M3內核微控制器數據手冊

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for Peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog Peripherals.

    標簽: Cortex-M 1850 LPC 內核微控制器

    上傳時間: 2014-12-31

    上傳用戶:zhuoying119

  • LPC4300系列ARM雙核微控制器產品數據手冊

    The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for Peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable Peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog Peripherals

    標簽: 4300 LPC ARM 雙核微控制器

    上傳時間: 2013-10-28

    上傳用戶:15501536189

  • 怎樣使用Nios II處理器來構建多處理器系統

    怎樣使用Nios II處理器來構建多處理器系統 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems  . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites   . . . . . . . . . . .  . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing   . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors   . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System   . . . . . . . . . . . . . . . . . 1–4 Sharing Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–7 Sharing Peripherals   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs  . . . . . . . . . . . . . . . .  1–15 Design Example: The Dining Philosophers’ Problem   . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System   . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example   1–17 Viewing a Philosopher System   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 1–18 Philosopher System Pipeline Bridges  . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems   . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–21 Connecting the Philosopher Subsystems  . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System   . . . . . . . . . . . . . . . . . .. 1–28

    標簽: Nios 處理器 多處理器

    上傳時間: 2013-11-21

    上傳用戶:lo25643

  • SL811開發資料_包含源程序_電路圖_芯片資料

    SL811開發資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB Peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.

    標簽: 811 SL 開發資料 源程序

    上傳時間: 2013-12-22

    上傳用戶:a82531317

  • This book introduces embedded systems to C and C++ programmers. Topics include testing memory device

    This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing Flash memory, verifying nonvolatile memory contents, controlling on-chip Peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty. Pages : 336 Slots : 1

    標簽: programmers introduces embedded include

    上傳時間: 2013-12-10

    上傳用戶:shizhanincc

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