Self timed Pipelined adder
標簽： Pipelined timed adder Self
上傳時間： 2014-01-10
上傳用戶：lgnf
Computer Architecture Pipelined implementation simulator
標簽： implementation Architecture Pipelined simulator
上傳時間： 2016-03-18
上傳用戶：sy_jiadeyi
On a distributed algorithm based on FPGA Pipelined FIR filter of the article.
標簽： distributed algorithm Pipelined article
上傳時間： 2017-08-18
上傳用戶：liuchee
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier
標簽： Counterflow-Pipelined Asynchronous Multiplier Scalable
上傳時間： 2014-01-04
上傳用戶：jjj0202
設計了一種用于高速ADC中的高速高增益的全差分CMOS運算放大器。主運放采用帶開關電容共模反饋的折疊式共源共柵結構，利用增益提高和三支路電流基準技術實現一個可用于12~14 bit精度，100 MS/s采樣頻率的高速流水線（Pipelined）ADC的運放。設計基于SMIC 0.25 μm CMOS工藝，在Cadence環境下對電路進行Spectre仿真。仿真結果表明，在2.5 V單電源電壓下驅動2 pF負載時，運放的直流增益可達到124 dB，單位增益帶寬720 MHz，轉換速率高達885 V/μs，達到0.1%的穩定精度的建立時間只需4 ns，共模抑制比153 dB。
上傳時間： 2014-12-23
上傳用戶：jiiszha
設計了一種用于高速ADC中的全差分套筒式運算放大器.從ADC的應用指標出發,確定了設計目標,利用開關電容共模反饋、增益增強等技術實現了一個可用于12 bit精度、100 MHz采樣頻率的高速流水線(Pipelined)ADC中的運算放大器.基于SMIC 0.13 μm,3.3 V工藝,Spectre仿真結果表明,該運放可以達到105.8 dB的增益,單位增益帶寬達到983.6 MHz,而功耗僅為26.2 mW.運放在4 ns的時間內可以達到0.01%的建立精度,滿足系統設計要求.
上傳時間： 2013-10-16
上傳用戶：563686540
DFT(Discrete Fourier Transformation)是數字信號分析與處理如圖形、語音及圖像等領域的重要變換工具，直接計算DFT的計算量與變換區間長度N的平方成正比。當N較大時，因計算量太大，直接用DFT算法進行譜分析和信號的實時處理是不切實際的。快速傅立葉變換(Fast Fourier Transformation，簡稱FFT)使DFT運算效率提高1～2個數量級。其原因是當N較大時，對DFT進行了基4和基2分解運算。FFT算法除了必需的數據存儲器ram和旋轉因子rom外，仍需較復雜的運算和控制電路單元，即使現在,實現長點數的FFT仍然是很困難。本文提出的FFT實現算法是基于FPGA之上的，算法完成對一個序列的FFT計算，完全由脈沖觸發，外部只輸入一脈沖頭和輸入數據，便可以得到該脈沖頭作為起始標志的N點FFT輸出結果。由于使用了雙ram，該算法是流型(Pipelined)的，可以連續計算N點復數輸入FFT，即輸入可以是分段N點連續復數數據流。采用DIF(Decimation In Frequency)-FFT和DIT(Decimation In Time)-FFT對于算法本身來說是無關緊要的，因為兩種情況下只是存儲器的讀寫地址有所變動而已，不影響算法的結構和流程，也不會對算法復雜度有何影響。
標簽： Transformation Discrete Fourier DFT
上傳時間： 2016-04-12
上傳用戶：lx9076
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/Pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.
標簽： implementation twofish cipher VHDL
上傳時間： 2017-06-25
上傳用戶：王小奇
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with Pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
標簽： communication important different channels
上傳時間： 2013-12-08
上傳用戶：litianchu
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully Pipelined for maximum throughput.
標簽： e.g. communication Transform important
上傳時間： 2017-06-25
上傳用戶：gxf2016
