基于MC145159的Pll頻率合成器設(shè)計(jì)與實(shí)現(xiàn)
介紹了鎖相環(huán)路頻率合成器的基本原理,分析了集成鎖相環(huán)芯片M C 145159的工作特性,給出了集成鎖相環(huán)芯片M C 145159的一個(gè)應(yīng)用實(shí)例,為高頻頻率合成器的設(shè)計(jì)提供了一個(gè)較好的思路.測試結(jié)果證明了設(shè)計(jì)的合理性與實(shí)用性,系統(tǒng)頻率穩(wěn)定度優(yōu)于10-7.
Jitter is extremely important in systems using Pll-based
clock drivers. The effects of jitter range from not having any
effect on system operation to rendering the system completely
non-functional. This application note provides the reader
with a clear understanding of jitter in high-speed systems. It
introduces the reader to various kinds of jitter in high-speed
systems, their causes and their effects, and methods of reducing
jitter. This application note will concentrate on jitter in Pll-based frequency synthesizers.
Cypress Semiconductor makes a variety of Pll-based clock
generators. This application note provides a set of recommendations
to optimize usage of Cypress clock devices in a
system. The application note begins with recommended termination
techniques for clock generators. Subsequently, power
supply filtering and bypassing is discussed. Finally, the application
note provides some recommendations on board
layout.
