This paper presents a low-Power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a Power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be Powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
Accurate estimates of the autocorrelation or Power spectrum can be obtained with a parametric model (AR, MA or ARMA). With automatic inference, not only the model parameters but also the model structure are determined from the data. It is assumed that the ARMASA toolbox is presen
Capacity of a MIMO channel with nt transmit antenna and nr recieve antenna is analyzed. The Power in parallel channel (after decomposition) is distributed as water-filling algorithm
