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using judgement on average power overflow or too small to implement the ProtectIOn on amplifier
標(biāo)簽： ProtectIOn judgement amplifier implement
上傳時(shí)間： 2013-12-27
上傳用戶：頂?shù)弥?/p>
LPC2214 Chip ProtectIOn
標(biāo)簽： ProtectIOn 2214 Chip LPC
上傳時(shí)間： 2013-12-11
上傳用戶：yph853211
保護(hù)模式教程源碼 The source code of ProtectIOn mode in dos
標(biāo)簽： ProtectIOn source code mode
上傳時(shí)間： 2013-12-24
上傳用戶：siguazgb
Optional time to see their dog timer, with ProtectIOn
標(biāo)簽： ProtectIOn Optional their timer
上傳時(shí)間： 2017-02-11
上傳用戶：515414293
e-book Fundamentals of Power System ProtectIOn
標(biāo)簽： Fundamentals ProtectIOn e-book System
上傳時(shí)間： 2017-04-01
上傳用戶：龍飛艇
Automatic ProtectIOn in Multicast networks
標(biāo)簽： ProtectIOn Automatic Multicast networks
上傳時(shí)間： 2013-12-22
上傳用戶：腳趾頭
It is the .exe version of file ProtectIOn via biometric key.
標(biāo)簽： ProtectIOn biometric version file
上傳時(shí)間： 2017-09-20
上傳用戶：TRIFCT
The challenges associated with the design and implementation of Electro- static Discharge (ESD) ProtectIOn circuits become increasingly complex as technology is scaled well into nano-metric regime. One must understand the behavior of semiconductor devices under very high current densities, high temperature transients in order to surmount the nano-meter ESD challenge. As a consequence, the quest for suitable ESD solution in a given technology must start from the device level. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions.
標(biāo)簽： ProtectIOn Circuit Device Design ESD and
上傳時(shí)間： 2020-06-05
上傳用戶：shancjb
Construction Strategy of ESD ProtectIOn CircuitAbstract： The principles used to construct ESD ProtectIOn on circuits and the basic conceptions of ESD ProtectIOn design are presented.Key words：ESD ProtectIOn/On circuit, ESD design window, ESD current path1 引言靜電放電（ESD，Electrostatic Discharge）給電子器件環(huán)境會(huì)帶來(lái)破壞性的后果。它是造成集成電路失效的主要原因之一。隨著集成電路工藝不斷發(fā)展，互補(bǔ)金屬氧化物半導(dǎo)體（CMOS，Complementary Metal-Oxide Semiconductor）的特征尺寸不斷縮小，金屬氧化物半導(dǎo)體(MOS, Metal-Oxide Semiconductor)的柵氧厚度越來(lái)越薄，MOS 管能承受的電流和電壓也越來(lái)越小，因此要進(jìn)一步優(yōu)化電路的抗ESD 性能，需要從全芯片ESD 保護(hù)結(jié)構(gòu)的設(shè)計(jì)來(lái)進(jìn)行考慮。
標(biāo)簽： Construction Strategy ESD of
上傳時(shí)間： 2013-11-09
上傳用戶：Aidane
Linear Technology’s high performance battery management ICsenable long battery life and run time, while providing precision charging control, constantstatus monitoring and stringent battery ProtectIOn. Our proprietary design techniques seamlesslymanage multiple input sources while providing small solution footprints, faster charging and100% standalone operation. Battery and circuit ProtectIOn features enable improved thermalperformance and high reliability operation.
上傳時(shí)間： 2013-10-13
上傳用戶：yyq123456789
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