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This book is for students and Linux System Administrators. It Provides the skills to read, write, and debug Linux shell scripts using bash shell. The book begins by describing Linux and simple scripts to automate frequently executed commands and continues by describing conditional logic, user interaction, loops, menus, traps, and functions.
上傳時(shí)間： 2014-12-30
上傳用戶(hù)：黃蛋的蛋黃
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, Provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時(shí)間： 2013-11-07
上傳用戶(hù)：swing
Abstract: The process of designing a radio system can be complex and often involves many project tradeoffs. Witha little insight, balancing these various characteristics can make the job of designing a radio system easier. Thistutorial explores these tradeoffs and Provides details to consider for various radio applications. With a focus on theindustrial, scientific, medical (ISM) bands, the subjects of frequency selection, one-way versus two-way systems,modulation techniques, cost, antenna options, power-supply influences, effects on range, and protocol selectionare explored.
標(biāo)簽： 無(wú)線(xiàn)
上傳時(shí)間： 2013-12-13
上傳用戶(hù)：eastgan
Abstract: This application note discusses a design for a phantom antenna power-supply system compatible with theDigital Satellite Equipment Control (DiSEqC) communication standard, using the MAX16948 automotive dual, highvoltageLDO/switch. The presented application circuit Provides a remote antenna power supply and also enables onewaycommunication from the radio head unit to the remote antenna. This system architecture offers flexibility inDiSEqC tone-burst frequency choice (100Hz to 30kHz), enabling users the ability to select the best frequency for theirapplication.
標(biāo)簽： 數(shù)字衛(wèi)星 控制 兼容 供電系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-17
上傳用戶(hù)：fnhhs
Abstract: With industrial/scientific/medical (ISM) band radio frequency (RF) products, often times users are new to the structure of Maxim's low pin-count transmitters andfully integrated superheterodyne receivers. This tutorial Provides simple steps that can be taken to get the best performance out of these transmitters and receivers whileproviding techniques to measure the overall capability of the design.
標(biāo)簽： ISM RF 無(wú)線(xiàn)電頻率
上傳時(shí)間： 2013-11-02
上傳用戶(hù)：yph853211
This document is a quick reference to some of the formulas and important information related to optical technologies. It focuses on decibels (dB), decibels per milliwatt (dBm), attenuation and measurements, and Provides an introduction to optical fibers.
上傳時(shí)間： 2013-10-17
上傳用戶(hù)：libenshu01
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that Provides dynamic clock gating and scaling.
上傳時(shí)間： 2013-10-11
上傳用戶(hù)：yuchunhai1990
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that Provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶(hù)：Altman
This example Provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶(hù)：yy_cn
MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評(píng)估板 軟件
上傳時(shí)間： 2013-10-24
上傳用戶(hù)：teddysha
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