·詳細(xì)說(shuō)明：對(duì)彩色車(chē)牌圖象的截取與識(shí)別 包括灰度化，均衡，除噪．截取等文件列表: 車(chē)牌識(shí)辨源程序 ..............\Debug ..............\ReadMe.txt ..............\Reconize.aps ..............\Reconize.clw .......
上傳時(shí)間： 2013-04-24
上傳用戶(hù)：waitingfy
LPC178* 177*用戶(hù)手冊(cè) LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 3 — 27 December 2011 Objective data sheet
上傳時(shí)間： 2013-04-24
上傳用戶(hù)：胡佳明胡佳明
olfile readme file. [1. 文件名解釋] olfile: Offload File 這個(gè)工具原本是項(xiàng)目中為測(cè)試TOE引擎的效率而設(shè)計(jì)的， 可以作為socket編程的一個(gè)例子來(lái)學(xué)習(xí)。 [2. 文件介紹] 程序中使用socket實(shí)現(xiàn)了文件的傳輸。
上傳時(shí)間： 2013-05-24
上傳用戶(hù)：ryb
MSP430FR57xx Family User's Guide (Rev. A)
上傳時(shí)間： 2013-11-15
上傳用戶(hù)：ainimao
msp430單片機(jī)
標(biāo)簽： Erratasheet 14x x14 Device
上傳時(shí)間： 2013-10-19
上傳用戶(hù)：dick_sh
TI公司低功耗單片機(jī)MSP430系列。
標(biāo)簽： MSP 430 Microcontroller Signal
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：非衣2016
24cxx讀寫(xiě)程序軟件-中文版 版本：V1.1.0.20916增加功能：用戶(hù)可以設(shè)置并口地址 可以編輯Client區(qū)內(nèi)容 修改了Client區(qū)界面 簡(jiǎn)體中文，英文雙語(yǔ)界面 詳見(jiàn)安裝好后的Readme.pdf-----------------------------------說(shuō)明：W24CXX.EXE為Windwos下使用計(jì)算機(jī)并口讀寫(xiě)24系列I2C EEPROM的小軟件開(kāi)發(fā)工具：Borland C++ Builder 6.0 WinDriver 5.05b開(kāi)發(fā)環(huán)境：Windows 2K Profressional SP3運(yùn)行環(huán)境：Windows98/NT/2K/XP-----------------------------------程序開(kāi)發(fā)：林曉斌（SONICSS)EMAIL: SONICSS@CNUNINET.COM注：若您使用Win98系統(tǒng)，必須重新啟動(dòng)計(jì)算機(jī)
上傳時(shí)間： 2013-11-10
上傳用戶(hù)：wxnumen
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶(hù)：fdmpy
ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VHDL ZBT
上傳時(shí)間： 2013-11-24
上傳用戶(hù)：31633073
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時(shí)間： 2013-11-13
上傳用戶(hù)：takako_yang
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