User ManualRev. 1.2SmartRF® CC2420DK: Packet Sniffer for IEEE 802.15.4 and ZigBee Table of contents1 INTRODUCTION...............................................................................................31.1 HARDWARE PLATFORM.......................................................................................31.2 SOFTWARE.........................................................................................................32 USER INTERFACE..........................................................................................42.1 MENUS AND TOOLBARS.......................................................................................62.2 SETUP................................................................................................................62.3 SELECT FIELDS...................................................................................................72.3.1 Tips............................................................................................................72.4 PACKET DETAILS.................................................................................................72.5 ADDRESS BOOK..................................................................................................92.5.1 Tips............................................................................................................92.6 DISPLAY FILTER................................................................................................102.7 TIME LINE.........................................................................................................103 HELP....................................................................................................................114 TROUBLESHOOTING..................................................................................125 GENERAL INFORMATION........................................................................135.1 DOCUMENT HISTORY........................................................................................135.2 DISCLAIMER......................................................................................................135.3 TRADEMARKS...................................................................................................136 ADDRESS INFORMATION........................................................................14
標(biāo)簽： 數(shù)據(jù) 分析儀 說明書
上傳時間： 2014-01-14
上傳用戶：zhangyi99104144
The Maxim Integrated 71M6541-DB REV 3.0 Demo Board is a demonstration board for evaluating the 71M6541 device for single-phase electronic energy metering applications in conjunction with the Remote Sensor Inter-face. It incorporates a 71M6541 integrated circuit, a 71M6601 Remote Interface IC, peripheral circuitry such as a serial EEPROM, emulator port, and on-board power supply. A serial to USB converter allows communication to a PC through a USB port. The Demo Board allows the evaluation of the 71M6541 energy meter chip for measurement accuracy and overall system use.
上傳時間： 2013-11-06
上傳用戶：雨出驚人love
介紹這一章介紹ARMTDMI-S 處理器包含以下小節(jié) 關(guān)于ARM7TDMI-S 處理器 ARM7TDMI-S 結(jié)構(gòu) ARM7TDMI-S 模塊內(nèi)核和功能框圖 ARM7TDMI-S 指令集匯總 Rev 3a 和Rev 4 之間的差異1.1 關(guān)于ARM7TDMI-S 處理器ARM7TDMI-S 處理器是ARM 通用32 位微處理器家族的成員之一ARM 處理器具有優(yōu)異的性能但功耗卻很低使用門的數(shù)量也很少ARM 結(jié)構(gòu)是基于精簡指令集計算機(jī)(RISC)原理而設(shè)計的指令集和相關(guān)的譯碼機(jī)制比復(fù)雜指令集計算機(jī)要簡單得多這樣的簡化實現(xiàn)了 高的指令吞吐量 出色的實時中斷響應(yīng) 小的高性價比的處理器宏單元
標(biāo)簽： arm7tdmi
上傳時間： 2014-12-30
上傳用戶：xiaowei314
§培訓(xùn)目標(biāo)： 本課程主要對EVDO的基本原理和關(guān)鍵技術(shù)進(jìn)行介紹。通過本課程的學(xué)習(xí)，可以了解EVDO Rev.0和Rev.A的空中接口和關(guān)鍵技術(shù)，以及1X/DO互操作的相關(guān)規(guī)則等。 §培訓(xùn)內(nèi)容： EVDO技術(shù)發(fā)展、網(wǎng)絡(luò)結(jié)構(gòu)簡介; EVDO Rev.0和RevA的空中接口結(jié)構(gòu); EVDO Rev.0和RevA的關(guān)鍵技術(shù); 1X / DO互操作原則;
標(biāo)簽： EVDO 關(guān)鍵技術(shù)
上傳時間： 2014-03-25
上傳用戶：d815185728
C++在幾乎所有的計算環(huán)境中都非常普及，而且可以用于幾乎所有的應(yīng)用程序。C++從C中繼承了過程化編程的高效性，并集成了面向?qū)ο缶幊痰墓δ堋++在其標(biāo)準(zhǔn)庫中提供了大量的功能。有許多商業(yè)C++庫支持?jǐn)?shù)量眾多的操作系統(tǒng)環(huán)境和專業(yè)應(yīng)用程序。但因為它的內(nèi)容太多了，所以掌握C++并不十分容易。本書詳述了C++語言的各個方面，包括數(shù)據(jù)類型、程序控制、函數(shù)、指針、調(diào)試、類、重載、繼承、多態(tài)性、模板、異常和輸入輸出等內(nèi)容。每一章都以前述內(nèi)容為基礎(chǔ)，每個關(guān)鍵點都用具體的示例進(jìn)行詳細(xì)的講解。本書基本不需要讀者具備任何C++知識，書中包含了理解C++的所有必要知識，讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語言編程經(jīng)驗但希望全面掌握C++語言的讀者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載
標(biāo)簽： 源代碼
上傳時間： 2013-11-18
上傳用戶：gaoqinwu
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-23
上傳用戶：shen_dafa
ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VHDL ZBT
上傳時間： 2013-10-25
上傳用戶：peterli123456
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時間： 2013-10-23
上傳用戶：半熟1994
個人求職管理系統(tǒng)》可以讓你在找工作的過程中方便地記錄你所選中的公司信息、職位信息、發(fā)送的簡歷和公司的回復(fù)，支持多用戶，是一個多用戶系統(tǒng)。具體請看readme文件。
標(biāo)簽： 管理系統(tǒng) 發(fā)送 過程 記錄
上傳時間： 2013-12-09
上傳用戶：it男一枚
功能：給出一個字符串表達(dá)式(可以是任意復(fù)雜的字符串表達(dá)式)，計算字符串表達(dá)式的值. <br> 特性： <br> 1：用戶可以添加其它運算符號 ，也就是說用戶可以制定新的運算符，引擎中不存在的運算符號，當(dāng)然具體的運算類還是得用戶提供. <br> 2: 可以修改運算符的性質(zhì)，你可以使得3*3=6，只要將*的運算類指向expression.DAdd就可以了,具體如何操作，ReadMe中有說明.<br> 3:可以使操作符運算具有多種形態(tài)。您即可以用“+”表示加法運算，也可以用" 加法" 表示加法運算.<br> 強(qiáng)調(diào)一下：,本引擎的最大特點就是： 用戶可以添加自己的運算符號，而無需修改計算引擎本身.<br>
上傳時間： 2015-01-18
上傳用戶：WMC_geophy
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