The emphasis of this book is on REAL-time application of Synopsys tools, used
to combat various problems seen at VDSM geometries. Readers will be
exposed to an effective design methodology for handling complex, submicron
ASIC designs. Significance is placed on HDL coding styles,
synthesis and optimization, dynamic simulation, formal verification, DFT
scan insertion, links to layout, physical synthesis, and static timing analysis.
At each step, problems related to each phase of the design flow are identified,
with solutions and work-around described in detail. In addition, crucial issues
related to layout, which includes clock tree synthesis and back-end
integration (links to layout) are also discussed at length. Furthermore, the
book contains in-depth discussions on the basics of Synopsys technology
libraries and HDL coding styles, targeted towards optimal synthesis solution.
This program is to find the floating point representation of REAL number.
The user will be asked for the number of mantissa, exponential, and the REAL number to be calculated (R=10).
The program will find the FPR for Hexadecimal (R=16), Octal (R=8), and Binary (R=2).
Some of the contents of this paper are adapted from the author’s book REAL-Time UML:
Developing Efficient Objects for Embedded Systems published by Addison-Wesley, 1998.
