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Reduced

Information technology – Small computer system interface (SCSI) – Part 326: Reduced block command

Information technology – Small computer system interface (SCSI) – Part 326: Reduced block commands (RBC)

標(biāo)簽： Information technology interface computer

上傳時(shí)間： 2013-12-25

上傳用戶(hù)：wsf950131
Code for calculating Reduced PAPR through SLM

Code for calculating Reduced PAPR through SLM

標(biāo)簽： calculating Reduced through Code

上傳時(shí)間： 2017-09-20

上傳用戶(hù)：851197153
地面數(shù)字電視廣播系統(tǒng)中SRRC濾波器及FFT處理器的設(shè)計(jì)與FPGA實(shí)現(xiàn).rar

隨著人們對(duì)數(shù)字電視和數(shù)字視頻信息的需求越來(lái)越大，數(shù)字電視廣播在中國(guó)迅速的發(fā)展起來(lái)。近幾年，數(shù)字電視傳輸系統(tǒng)技術(shù)逐漸成熟，數(shù)字電視地面廣播（DTTB）傳輸標(biāo)準(zhǔn)也于2006年8月30號(hào)正式出臺(tái)。此標(biāo)準(zhǔn)技術(shù)是由我國(guó)多家單位聯(lián)合研究的，具有自主知識(shí)產(chǎn)權(quán)的數(shù)字地面電視傳輸標(biāo)準(zhǔn)。DTTB系統(tǒng)標(biāo)準(zhǔn)的研究與仿真，具有巨大的實(shí)用價(jià)值和廣闊的市場(chǎng)前景。 @@ 本文首先研究了地面數(shù)字電視廣播標(biāo)準(zhǔn)中平方根升余弦（SRRC）濾波器（滾降系數(shù)為0．05）的結(jié)構(gòu)設(shè)計(jì)，介紹了一種適合在FPGA中實(shí)現(xiàn)的高階高速FIR濾波器的并行流水線(xiàn)結(jié)構(gòu)。在本設(shè)計(jì)中，以CSD數(shù)優(yōu)化濾波器系數(shù)，并運(yùn)用簡(jiǎn)化加法器圖（Reduced Adder Graph，RAG）算法進(jìn)行改進(jìn)，最后采用并行處理的轉(zhuǎn)置型流水線(xiàn)結(jié)構(gòu)實(shí)現(xiàn)。 @@ 接著研究數(shù)字電視地面?zhèn)鬏敇?biāo)準(zhǔn)采用的傳輸技術(shù)-OFDM的基本概念和技術(shù)特點(diǎn)，并研究了清華大學(xué)提出的DMB-T方案中TDS-OFDM信號(hào)幀的組成結(jié)構(gòu)以及相關(guān)原理。 @@ 最后，本文針對(duì)OFDM調(diào)制所需要的3780點(diǎn)FFT處理器進(jìn)行研究。為了保證OFDM信號(hào)的采樣率和時(shí)域?qū)ьl的采樣率相同，以達(dá)到較好的同步性能，采用了3780個(gè)正交子載波的設(shè)計(jì)方案。在實(shí)現(xiàn)過(guò)程中，分析比較了多種算法的計(jì)算復(fù)雜性，設(shè)計(jì)出在硬件實(shí)現(xiàn)復(fù)雜度上進(jìn)行優(yōu)化的3780點(diǎn)FFT處理器的數(shù)據(jù)流流水線(xiàn)算法。之后，通過(guò)定點(diǎn)仿真比較各模塊輸出的動(dòng)態(tài)范圍和概率分布，設(shè)計(jì)出定點(diǎn)字長(zhǎng)的優(yōu)化方案，并分析計(jì)算了這一處理器的輸出信噪比與內(nèi)部各模塊字長(zhǎng)的關(guān)系，進(jìn)一步降低了硬件實(shí)現(xiàn)復(fù)雜性。 @@關(guān)鍵字：數(shù)字電視地面廣播傳輸（DTTB）；平方根升余弦濾波器（SRRC）；正交頻分復(fù)用調(diào)制（OFDM）；快速傅立葉變換（FFT）； 3780

標(biāo)簽： SRRC FPGA FFT

上傳時(shí)間： 2013-04-24

上傳用戶(hù)：mdrd3080
D類(lèi)數(shù)字輸入放大器的簡(jiǎn)化系統(tǒng)設(shè)計(jì)

Abstract: This application note describes a new generation of digital-input Class D audio amplifiers that achieve high PSRRperformance, comparable to traditional analog Class D amplifiers. More importantly, these digital-input Class D amplifiersprovide additional benefits of Reduced power, complexity, noise, and system cost.

標(biāo)簽： 數(shù)字輸入放大器系統(tǒng)設(shè)計(jì)

上傳時(shí)間： 2013-12-20

上傳用戶(hù)：JIUSHICHEN
COOLMOS全面認(rèn)識(shí)

Recently a new technology for high voltage Power MOSFETshas been introduced – the CoolMOS™ . Based on thenew device concept of charge compensation the RDS(on) areaproduct for e.g. 600V transistors has been Reduced by afactor of 5. The devices show no bipolar current contributionlike the well known tail current observed during the turn-offphase of IGBTs. CoolMOS™ virtually combines the lowswitching losses of a MOSFET with the on-state losses of anIGBT.

標(biāo)簽： COOLMOS

上傳時(shí)間： 2013-11-14

上傳用戶(hù)：zhyiroy
LTC1062的低通濾波器應(yīng)用

Highlights the LTC1062 as a lowpass filter in a phase lock loop. Describes how the loop's bandwidth can be increased and the VCO output jitter Reduced when the LTC1062 is the loop filter. Compares it with a passive RC loop filter. Also discussed is the use of LTC1062 as simple bandpass and bandstop filter.

標(biāo)簽： 1062 LTC 低通濾波器

上傳時(shí)間： 2013-10-24

上傳用戶(hù)：chens000
DN460雙輸出降壓穩(wěn)壓器優(yōu)化效率

The LTC3546 is a dual output current mode buck regulatorwith fl exible output current partitioning. Beyondthe advantages normally associated with dual outputregulators (Reduced size, cost, EMI and part count, withimproved effi ciency), the LTC3546’s outputs can bepartitioned for either 3A and 1A outputs, or two 2A outputs.This increases its application range and simplifi esmultiple supply rail designs. A confi gurable Burst Mode®clamp for each output sets the current transition levelbetween Burst Mode operation and forced continuousconduction mode to optimize effi ciency over the entireoutput range. An adjustable switching frequency up to4MHz and internal power MOSFET switches allow forsmall and compact footprints.

標(biāo)簽： 460 DN 輸出優(yōu)化效率

上傳時(shí)間： 2013-11-04

上傳用戶(hù)：yxgi5
基于單片機(jī)系統(tǒng)的(24,16)循環(huán)碼編碼、譯碼方案

　　在理論分析循環(huán)碼編碼和譯碼基本原理的基礎(chǔ)上，提出了基于單片機(jī)系統(tǒng)的(24，16)循環(huán)碼軟件實(shí)現(xiàn)編碼、譯碼的方案。仿真結(jié)果表明(24，16)循環(huán)碼能有效地克服來(lái)自通訊信道的干擾，保證數(shù)據(jù)通信的可靠及系統(tǒng)的穩(wěn)定，使誤碼率大幅度降低。本論文對(duì)(24，16)循環(huán)碼的研究結(jié)果表明，可以有效地降低錯(cuò)誤概率和提高系統(tǒng)的吞吐量，實(shí)現(xiàn)糾錯(cuò)僅需要在接收端增加有限的存儲(chǔ)空間和計(jì)算復(fù)雜度，具有一定的實(shí)用價(jià)值。　　Abstract: 　　Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be Reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.

標(biāo)簽： 24 16 單片機(jī)系統(tǒng) 循環(huán)碼

上傳時(shí)間： 2013-11-09

上傳用戶(hù)：gaoliangncepu
Virtex-5, Spartan-DSP FPGAs Ap

Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and Reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.

標(biāo)簽： Spartan-DSP Virtex FPGAs Ap

上傳時(shí)間： 2013-10-23

上傳用戶(hù)：raron1989
PIC16f877快速入門(mén)教程

雖然PIC都是8位的單片機(jī)，但都采用RISC（Reduced Instruction Set Computing）核心結(jié)構(gòu)，這有別于過(guò)去一般的CISC(Complex Instruction Set Computing)結(jié)構(gòu)。所謂RISC結(jié)構(gòu)就是采用哈佛雙總線(xiàn)結(jié)構(gòu)，將地址總線(xiàn)與數(shù)據(jù)總線(xiàn)分開(kāi)，因此在同一個(gè)指令執(zhí)行過(guò)程中，數(shù)據(jù)與地址可以同時(shí)傳送，避免了總線(xiàn)處理上的瓶頸。

標(biāo)簽： f877 PIC 16f 877

上傳時(shí)間： 2013-11-21

上傳用戶(hù)：tianyi223

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Reduced

Information technology – Small computer system interface (SCSI) – Part 326: Reduced block command

Code for calculating Reduced PAPR through SLM

地面數(shù)字電視廣播系統(tǒng)中SRRC濾波器及FFT處理器的設(shè)計(jì)與FPGA實(shí)現(xiàn).rar

D類(lèi)數(shù)字輸入放大器的簡(jiǎn)化系統(tǒng)設(shè)計(jì)

COOLMOS全面認(rèn)識(shí)

LTC1062的低通濾波器應(yīng)用

DN460雙輸出降壓穩(wěn)壓器優(yōu)化效率

基于單片機(jī)系統(tǒng)的(24,16)循環(huán)碼編碼、譯碼方案

Virtex-5, Spartan-DSP FPGAs Ap

PIC16f877快速入門(mén)教程