ST7529液晶驅動 The ST7529 is a driver & controller LSI for 32 gray scale graphic dot-matrix liquid crystal display systems. It generates 255 Segment and 160 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), 8-bit/16-bit parallel or IIC display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
標簽： 7529 controller dot-matrix graphic
上傳時間： 2013-12-02
上傳用戶：奇奇奔奔
This manual describes Freescale’s IEEE™ 802.15.4 Standard compliant MAC/PHY software. The Freescale 802.15.4 MAC/PHY software is designed for use with the Freescale MC1319x and MC1320x, family of short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers, designed for use with the HCS08 Family of MCUs. The MAC/PHY software also works with the MC1321x family of short range, low power, 2.4 GHz ISM band transceivers that incorporate a low power 2.4 GHz radio frequency transceiver and an 8-bit microcontroller into a single LGA package. Throughout this manual, the term transceiver refers to either the MC1319x, MC1320x, or the internal counterpart inside the MC1321x System in a Package (SiP).
標簽： Freescale describes compliant Standard
上傳時間： 2016-04-17
上傳用戶：caiiicc
vhdl編寫，8b—10b 編解碼器設計 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
上傳時間： 2016-05-05
上傳用戶：gundamwzc
用verilog語言編寫，一個8-bit ALU，可以完成按字節的+、-和與、或、非操作
上傳時間： 2013-12-06
上傳用戶：妄想演繹師
摘自university of waterloo的個別知道筆記，主要關于electrical and computer engineering方面，包括了8-bit hamming的編解碼以及使用VHDL的硬件開發
標簽： university waterloo of
上傳時間： 2016-07-07
上傳用戶：qq521
[UsbKbd.rar] - usbkbd,用wdm編寫的usb和鍵盤的驅動示例 [USB2.0_USB_driver.rar] - 學習USB2.0驅動程序設計源碼，包括Windows DDK Driver驅動的詳細設計，U盤，MP3的程序設計例子 [mc8051_design.zip] - MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051
標簽： USB_driver USB 2.0
上傳時間： 2013-12-29
上傳用戶：xauthu
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標簽： Description Behavorial wb_master Filename
上傳時間： 2014-07-11
上傳用戶：zhanditian
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標簽： bus bidirectional primarily designed
上傳時間： 2013-12-11
上傳用戶：jeffery
iic總線控制器VHDL實現 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
標簽： VHDL c_control vhd control
上傳時間： 2016-10-30
上傳用戶：woshiayin
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
標簽： Microchip Routines Sample WRITE
上傳時間： 2013-12-27
上傳用戶：ljmwh2000
