兩種解決方案 Richard just finished building his new house. Now the only thing the house misses is a cute little wooden fence. He had no idea how to make a wooden fence, so he decided to order one. Somehow he got his hands on the ACME Fence Catalogue 2002, the ultimate resource on cute little wooden fences. After reading its preface he already knew, what makes a little wooden fence cute.
A wooden fence consists of N wooden planks, placed vertically in a row next to each other. A fence looks cute if and only if the following conditions are met:
?The planks have different lengths, namely 1, 2, . . . , N plank length units.
?Each plank with two neighbors is either larger than each of its neighbors or smaller than each of them. (Note that this makes the top of the fence alternately Rise and fall.)
標簽：
house
the
finished
building
上傳時間：
2014-01-26
上傳用戶：541657925
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of
Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input,
and ’1’ is output when the START signal Rises. Therefore, the FF data input is fixed at
the power supply, since the typical value ’1’ is output following the Rise of the START
signal.
When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan
may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower
part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that
the clock signal is input to the clock pin of the FF.
Other than the sample shown in Example 2-21, there are situations where for certain
control signals, those that had been switched due to the conditions of an external input
will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a
fixed value is input from an upper level, the input value of the FF may also end up being
fixed as the result of optimization with logic synthesis tools. In a situation like this, while
perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽：
RTL
verilog hdl
上傳時間：
2022-03-21
上傳用戶：canderile
