·詳細說明：C#環(huán)境的車牌認別系統(tǒng)源代碼和30張測試圖片；本程序?qū)σ陨系?0汽車圖片的認別定位分割等準確率達至100％。文件列表: SAMple ......\App.ico ......\AssemblyInfo.cs ......\bin ......\...\Debug ......\...\Release &
上傳時間： 2013-07-11
上傳用戶：changeboy
·詳細說明：韓國移動電視的測試源樣本， 是H264和AAC打包的- South Korea moves the television the test source SAMple, is H264 and AAC packs
上傳時間： 2013-05-28
上傳用戶：thuyenvinh
The 14-bit LTC2351-14 is a 1.5Msps, low power SARADC with six simultaneously SAMpled differential inputchannels. It operates from a single 3V supply and featuressix independent SAMple-and-hold amplifi ers and a singleADC. The single ADC with multiple S/HAs enables excellentrange match (1mV) between channels and channel-tochannelskew (200ps).
上傳時間： 2014-12-23
上傳用戶：天誠24
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromSAMple to SAMple. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時間： 2013-11-12
上傳用戶：pans0ul
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or SAMple. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標簽： Architecture ExpressTM PCI
上傳時間： 2013-11-03
上傳用戶：gy592333
A frequent requirement in systems involves drivinganalog signals into non-linear or reactive loads. Cables,transformers, actuators, motors and SAMple-hold circuitsare examples where the ability to drive diffi cult loads isrequired. Although several power buffer amplifi ers areavailable, none have been optimized for driving diffi cultloads.
上傳時間： 2014-12-24
上傳用戶：1109003457
Abstract: This application note describes how to build, debug, and run applications on the on-board MAXQ622microcontroller to interface with the DS8005 dual smart card interface. This is demonstrated in both IAREmbedded Workbench and the Rowley CrossWorks IDE, using SAMple code provided with the kit.
上傳時間： 2013-10-29
上傳用戶：ddddddd
介紹一種基于C8051F060單片機和NAND Flash的數(shù)據(jù)采集存儲系統(tǒng)，該系統(tǒng)可實現(xiàn)3路信號采樣，每路采樣率為5KS/s,通過異步串行通信接口實現(xiàn)數(shù)據(jù)傳輸。并詳細說明系統(tǒng)的軟件設計。 Abstract: An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to SAMple three-channel of signal,5KSPS each channel,and can upload data to test bench through UART（Universal Asynchronous Receiver/Transmitter）.The software design is discussed in detail.
標簽： C8051F060 數(shù)據(jù)采集 存儲系統(tǒng)
上傳時間： 2013-10-12
上傳用戶：Jesse_嘉偉
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific SAMple points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive SAMples show different levels. Thus, only the current level of an input signalat these SAMple points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the SAMple rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is SAMpled throughsoftware every 10us, it is irrelevant, which input level would be seen between theSAMples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the SAMple rate of 10us, it is assured that only one SAMple canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, theSAMple rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a SAMple rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the SAMple rate is shown. The numbers 1 to 5 in thediagram represent possible SAMple points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the SAMple points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).SAMple points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be SAMpled here. If low is SAMpled, no transition willbe detected. If the SAMple results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous SAMple 2) had alreadydetected a high, there is no change. If the previous SAMple 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific SAMple points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive SAMples show different levels. Thus, only the current level of an input signalat these SAMple points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the SAMple rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is SAMpled throughsoftware every 10us, it is irrelevant, which input level would be seen between theSAMples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the SAMple rate of 10us, it is assured that only one SAMple canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, theSAMple rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a SAMple rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
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